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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 77 |
Rev 78 |
| Line 146... |
Line 146... |
always @ (posedge wbs_clk or posedge wbs_rst)
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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if (wbs_rst)
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wbs_eoc <= 1'b0;
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wbs_eoc <= 1'b0;
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else
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else
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
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wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
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wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
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else if (wbs_eoc_alert & (a_rd | a_wr))
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else if (wbs_eoc_alert & (a_rd | a_wr))
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wbs_eoc <= 1'b1;
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wbs_eoc <= 1'b1;
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`define MODULE cnt_shreg_ce_clear
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`define MODULE cnt_shreg_ce_clear
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`BASE`MODULE # ( .length(16))
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`BASE`MODULE # ( .length(16))
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| Line 348... |
Line 348... |
last_cyc <= wbm_cyc_o;
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last_cyc <= wbm_cyc_o;
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assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
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assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
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assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
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assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
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(wbm_bte_o==2'b10) ? 4'd8 :
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(wbm_bte_o==2'b10) ? 4'd8 :
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4'd16;
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(wbm_bte_o==2'b11) ? 4'd16:
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4'd1;
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assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
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assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
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assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
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assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
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assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
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assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
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`define MODULE wb3wb3_bridge
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`define MODULE wb3wb3_bridge
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| Line 371... |
Line 372... |
.wbs_ack_o(wbs_ack_o),
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.wbs_ack_o(wbs_ack_o),
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.wbs_clk(wbs_clk),
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.wbs_clk(wbs_clk),
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.wbs_rst(wbs_rst),
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.wbs_rst(wbs_rst),
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// wishbone master side
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// wishbone master side
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.wbm_dat_o(writedata),
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.wbm_dat_o(writedata),
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.wbm_adr_o(adress),
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.wbm_adr_o(address),
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.wbm_sel_o(be),
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.wbm_sel_o(be),
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.wbm_bte_o(wbm_bte_o),
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.wbm_bte_o(wbm_bte_o),
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.wbm_cti_o(wbm_cti_o),
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.wbm_cti_o(wbm_cti_o),
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.wbm_we_o(wbm_we_o),
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.wbm_we_o(wbm_we_o),
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.wbm_cyc_o(wbm_cyc_o),
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.wbm_cyc_o(wbm_cyc_o),
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