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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 77 and 78

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Rev 77 Rev 78
Line 146... Line 146...
always @ (posedge wbs_clk or posedge wbs_rst)
always @ (posedge wbs_clk or posedge wbs_rst)
if (wbs_rst)
if (wbs_rst)
        wbs_eoc <= 1'b0;
        wbs_eoc <= 1'b0;
else
else
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
        else if (wbs_eoc_alert & (a_rd | a_wr))
        else if (wbs_eoc_alert & (a_rd | a_wr))
                wbs_eoc <= 1'b1;
                wbs_eoc <= 1'b1;
 
 
`define MODULE cnt_shreg_ce_clear
`define MODULE cnt_shreg_ce_clear
`BASE`MODULE # ( .length(16))
`BASE`MODULE # ( .length(16))
Line 348... Line 348...
    last_cyc <= wbm_cyc_o;
    last_cyc <= wbm_cyc_o;
 
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    4'd16;
                    (wbm_bte_o==2'b11) ? 4'd16:
 
                    4'd1;
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
 
 
`define MODULE wb3wb3_bridge
`define MODULE wb3wb3_bridge
Line 371... Line 372...
    .wbs_ack_o(wbs_ack_o),
    .wbs_ack_o(wbs_ack_o),
    .wbs_clk(wbs_clk),
    .wbs_clk(wbs_clk),
    .wbs_rst(wbs_rst),
    .wbs_rst(wbs_rst),
    // wishbone master side
    // wishbone master side
    .wbm_dat_o(writedata),
    .wbm_dat_o(writedata),
    .wbm_adr_o(adress),
    .wbm_adr_o(address),
    .wbm_sel_o(be),
    .wbm_sel_o(be),
    .wbm_bte_o(wbm_bte_o),
    .wbm_bte_o(wbm_bte_o),
    .wbm_cti_o(wbm_cti_o),
    .wbm_cti_o(wbm_cti_o),
    .wbm_we_o(wbm_we_o),
    .wbm_we_o(wbm_we_o),
    .wbm_cyc_o(wbm_cyc_o),
    .wbm_cyc_o(wbm_cyc_o),

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