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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 90 and 91

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Rev 90 Rev 91
Line 56... Line 56...
output ack_o;
output ack_o;
input clk, rst;
input clk, rst;
 
 
reg [adr_width-1:0] adr;
reg [adr_width-1:0] adr;
wire [max_burst_width-1:0] to_adr;
wire [max_burst_width-1:0] to_adr;
 
reg [max_burst_width-1:0] last_adr;
 
reg [1:0] last_cycle;
 
localparam idle = 2'b00;
 
localparam cyc  = 2'b01;
 
localparam ws   = 2'b10;
 
localparam eoc  = 2'b11;
 
 
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    last_adr <= {max_burst_width{1'b0}};
 
else
 
    if (stb_i)
 
        last_adr <=adr_o;
 
 
generate
generate
if (max_burst_width==0) begin : inst_0
if (max_burst_width==0) begin : inst_0
    reg ack_o;
    reg ack_o;
    assign adr_o = adr_i;
    assign adr_o = adr_i;
Line 68... Line 81...
        ack_o <= 1'b0;
        ack_o <= 1'b0;
    else
    else
        ack_o <= cyc_i & stb_i & !ack_o;
        ack_o <= cyc_i & stb_i & !ack_o;
end else begin
end else begin
 
 
    reg [1:0] last_cycle;
 
    localparam idle = 2'b00;
 
    localparam cyc  = 2'b01;
 
    localparam ws   = 2'b10;
 
    localparam eoc  = 2'b11;
 
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        last_cycle <= idle;
        last_cycle <= idle;
    else
    else
        last_cycle <= (!cyc_i) ? idle :
        last_cycle <= (!cyc_i) ? idle :
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
                      (cyc_i & !stb_i) ? ws :
                      (cyc_i & !stb_i) ? ws :
                      cyc;
                      cyc;
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
 
                                        (!stb_i) ? last_adr :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
                                        adr[max_burst_width-1:0];
                                        adr[max_burst_width-1:0];
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
    assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
end
end
endgenerate
endgenerate
Line 124... Line 133...
if (max_burst_width==4) begin : inst_4
if (max_burst_width==4) begin : inst_4
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        adr <= 4'h0;
        adr <= 4'h0;
    else
    else
        if (cyc_i & stb_i)
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
            case (bte_i)
            case (bte_i)
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
            default: adr[3:0] <= to_adr + 4'd1;
            default: adr[3:0] <= to_adr + 4'd1;
            endcase
            endcase
Line 836... Line 845...
ram0(
ram0(
`undef MODULE
`undef MODULE
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(adr),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
    .re(wbs_stb_i),
 
    .we(wbs_we_i & wbs_ack_o),
    .we(wbs_we_i & wbs_ack_o),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
 
 

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