Line 57... |
Line 57... |
input clk, rst;
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input clk, rst;
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reg [adr_width-1:0] adr;
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reg [adr_width-1:0] adr;
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wire [max_burst_width-1:0] to_adr;
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wire [max_burst_width-1:0] to_adr;
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reg [max_burst_width-1:0] last_adr;
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reg [max_burst_width-1:0] last_adr;
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reg [1:0] last_cycle;
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reg last_cycle;
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localparam idle = 2'b00;
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localparam idle_or_eoc = 1'b0;
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localparam cyc = 2'b01;
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localparam cyc_or_ws = 1'b1;
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localparam ws = 2'b10;
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localparam eoc = 2'b11;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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last_adr <= {max_burst_width{1'b0}};
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last_adr <= {max_burst_width{1'b0}};
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else
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else
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if (stb_i)
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if (stb_i)
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last_adr <=adr_o;
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last_adr <=adr_o[max_burst_width-1:0];
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generate
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generate
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if (max_burst_width==0) begin : inst_0
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if (max_burst_width==0) begin : inst_0
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reg ack_o;
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reg ack_o;
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assign adr_o = adr_i;
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assign adr_o = adr_i;
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Line 83... |
Line 81... |
ack_o <= cyc_i & stb_i & !ack_o;
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ack_o <= cyc_i & stb_i & !ack_o;
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end else begin
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end else begin
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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last_cycle <= idle;
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last_cycle <= idle_or_eoc;
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else
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else
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last_cycle <= (!cyc_i) ? idle :
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last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
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(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
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(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
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(cyc_i & !stb_i) ? ws :
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(cyc_i & !stb_i) ? cyc_or_ws : //ws
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cyc;
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cyc_or_ws; // cyc
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assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
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assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
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(!stb_i) ? last_adr :
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(!stb_i) ? last_adr :
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(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
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(last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
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adr[max_burst_width-1:0];
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adr[max_burst_width-1:0];
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assign ack_o = (last_cycle==cyc | last_cycle==ws) & stb_i;
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assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
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end
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end
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endgenerate
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endgenerate
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generate
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generate
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if (max_burst_width==2) begin : inst_2
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if (max_burst_width==2) begin : inst_2
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Line 1047... |
Line 1045... |
assign wb_ack_o = wb_ack;
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assign wb_ack_o = wb_ack;
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endmodule
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endmodule
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`endif
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`endif
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`ifdef WB_DPRAM
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`ifdef WB_B3_DPRAM
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`define MODULE wb_dpram
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`define MODULE wb_b3_dpram
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module `BASE`MODULE (
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module `BASE`MODULE (
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`undef MODULE
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`undef MODULE
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// wishbone slave side a
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// wishbone slave side a
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wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
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wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
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wbsa_clk, wbsa_rst,
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wbsa_clk, wbsa_rst,
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// wishbone slave side a
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// wishbone slave side b
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wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
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wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
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wbsb_clk, wbsb_rst);
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wbsb_clk, wbsb_rst);
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parameter data_width = 32;
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parameter data_width_a = 32;
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parameter addr_width = 8;
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parameter data_width_b = data_width_a;
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parameter addr_width_a = 8;
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parameter dat_o_mask_a = 1;
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localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
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parameter dat_o_mask_b = 1;
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parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
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parameter max_burst_width_a = 4;
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input [31:0] wbsa_dat_i;
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parameter max_burst_width_b = max_burst_width_a;
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input [addr_width-1:2] wbsa_adr_i;
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input [data_width_a-1:0] wbsa_dat_i;
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input [addr_width_a-1:0] wbsa_adr_i;
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input [data_width_a/8-1:0] wbsa_sel_i;
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input [2:0] wbsa_cti_i;
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input [1:0] wbsa_bte_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
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output [31:0] wbsa_dat_o;
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output [data_width_a-1:0] wbsa_dat_o;
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output wbsa_ack_o;
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output wbsa_ack_o;
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input wbsa_clk, wbsa_rst;
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input wbsa_clk, wbsa_rst;
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input [31:0] wbsb_dat_i;
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input [data_width_b-1:0] wbsb_dat_i;
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input [addr_width-1:2] wbsb_adr_i;
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input [addr_width_b-1:0] wbsb_adr_i;
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input [data_width_b/8-1:0] wbsb_sel_i;
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input [2:0] wbsb_cti_i;
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input [1:0] wbsb_bte_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
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output [31:0] wbsb_dat_o;
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output [data_width_b-1:0] wbsb_dat_o;
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output wbsb_ack_o;
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output wbsb_ack_o;
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input wbsb_clk, wbsb_rst;
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input wbsb_clk, wbsb_rst;
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wire wbsa_dat_tmp, wbsb_dat_tmp;
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wire [addr_width_a-1:0] adr_a;
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wire [addr_width_b-1:0] adr_b;
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`define MODULE dpram_2r2w
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`define MODULE wb_adr_inc
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`BASE`MODULE # (
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`BASE`MODULE # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
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.cyc_i(wbsa_cyc_i),
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.stb_i(wbsa_stb_i),
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.cti_i(wbsa_cti_i),
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.bte_i(wbsa_bte_i),
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.adr_i(wbsa_adr_i),
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.we_i(wbsa_we_i),
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.ack_o(wbsa_ack_o),
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.adr_o(adr_a),
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.clk(wbsa_clk),
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.rst(wbsa_rst));
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`BASE`MODULE # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
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.cyc_i(wbsb_cyc_i),
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.stb_i(wbsb_stb_i),
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.cti_i(wbsb_cti_i),
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.bte_i(wbsb_bte_i),
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.adr_i(wbsb_adr_i),
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.we_i(wbsb_we_i),
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.ack_o(wbsb_ack_o),
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.adr_o(adr_b),
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.clk(wbsb_clk),
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.rst(wbsb_rst));
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`undef MODULE
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`define MODULE dpram_be_2r2w
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`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
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`undef MODULE
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`undef MODULE
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.data_width(data_width), .addr_width(addr_width) )
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ram_i (
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dpram0(
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.d_a(wbsa_dat_i),
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.d_a(wbsa_dat_i),
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.q_a(wbsa_dat_tmp),
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.q_a(wbsa_dat_o),
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.adr_a(wbsa_adr_i),
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.adr_a(adr_a),
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.we_a(wbsa_we_i),
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.be_a(wbsa_sel_i),
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.we_a(wbsa_we_i & wbsa_ack_o),
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.clk_a(wbsa_clk),
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.clk_a(wbsa_clk),
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.d_b(wbsb_dat_i),
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.d_b(wbsb_dat_i),
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.q_b(wbsb_dat_tmp),
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.q_b(wbsb_dat_o),
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.adr_b(wbsb_adr_i),
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.adr_b(adr_b),
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.we_b(wbsb_we_i),
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.be_b(wbsb_sel_i),
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.we_b(wbsb_we_i & wbsb_ack_o),
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.clk_b(wbsb_clk) );
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.clk_b(wbsb_clk) );
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generate if (dat_o_mask_a==1)
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assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
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endgenerate
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generate if (dat_o_mask_a==0)
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assign wbsa_dat_o = wbsa_dat_tmp;
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endgenerate
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generate if (dat_o_mask_b==1)
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assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
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endgenerate
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generate if (dat_o_mask_b==0)
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assign wbsb_dat_o = wbsb_dat_tmp;
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endgenerate
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`define MODULE spr
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`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
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`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
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`undef MODULE
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endmodule
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endmodule
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`endif
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`endif
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No newline at end of file
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No newline at end of file
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