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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 92 and 94

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Line 162... Line 162...
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // wishbone master side
        // wishbone master side
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
 
 
 
parameter style = "FIFO"; // valid: simple, FIFO
 
parameter addr_width = 4;
 
 
input [31:0] wbs_dat_i;
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [31:2] wbs_adr_i;
input [3:0]  wbs_sel_i;
input [3:0]  wbs_sel_i;
input [1:0]  wbs_bte_i;
input [1:0]  wbs_bte_i;
input [2:0]  wbs_cti_i;
input [2:0]  wbs_cti_i;
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output wbm_stb_o;
output wbm_stb_o;
input [31:0]  wbm_dat_i;
input [31:0]  wbm_dat_i;
input wbm_ack_i;
input wbm_ack_i;
input wbm_clk, wbm_rst;
input wbm_clk, wbm_rst;
 
 
parameter addr_width = 4;
 
 
 
// bte
// bte
parameter linear       = 2'b00;
parameter linear       = 2'b00;
parameter wrap4        = 2'b01;
parameter wrap4        = 2'b01;
parameter wrap8        = 2'b10;
parameter wrap8        = 2'b10;
parameter wrap16       = 2'b11;
parameter wrap16       = 2'b11;
// cti
// cti
parameter classic      = 3'b000;
parameter classic      = 3'b000;
parameter incburst     = 3'b010;
parameter incburst     = 3'b010;
parameter endofburst   = 3'b111;
parameter endofburst   = 3'b111;
 
 
parameter wbs_adr  = 1'b0;
localparam wbs_adr  = 1'b0;
parameter wbs_data = 1'b1;
localparam wbs_data = 1'b1;
 
 
parameter wbm_adr0      = 2'b00;
localparam wbm_adr0      = 2'b00;
parameter wbm_adr1      = 2'b01;
localparam wbm_adr1      = 2'b01;
parameter wbm_data      = 2'b10;
localparam wbm_data      = 2'b10;
parameter wbm_data_wait = 2'b11;
localparam wbm_data_wait = 2'b11;
 
 
reg [1:0] wbs_bte_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg wbs_eoc, wbm_eoc;
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    .clk_b(wbsb_clk) );
    .clk_b(wbsb_clk) );
 
 
endmodule
endmodule
`endif
`endif
 
 
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