| Line 1140... |
Line 1140... |
`endif
|
`endif
|
|
|
`ifdef WBB3_WBB4_CACHE
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`ifdef WBB3_WBB4_CACHE
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`define MODULE wbb3_wbb4_cache
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`define MODULE wbb3_wbb4_cache
|
module `BASE`MODULE (
|
module `BASE`MODULE (
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
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wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
);
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);
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`undef MODULE
|
`undef MODULE
|
|
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parameter dw_s = 32;
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parameter dw_s = 32;
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parameter aw_s = 24;
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parameter aw_s = 24;
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| Line 1156... |
Line 1156... |
parameter async = 1; // wbs_clk != wbm_clk
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parameter async = 1; // wbs_clk != wbm_clk
|
|
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parameter nr_of_ways = 1;
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parameter nr_of_ways = 1;
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parameter aw_offset = 4; // 4 => 16 words per cache line
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parameter aw_offset = 4; // 4 => 16 words per cache line
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parameter aw_slot = 10;
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parameter aw_slot = 10;
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localparam aw_tag = aw_s - aw_tag_mem - aw_offset;
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localparam aw_tag = aw_s - aw_slot - aw_offset;
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parameter wbm_burst_size = 4; // valid options 4,8,16
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parameter wbm_burst_size = 4; // valid options 4,8,16
|
|
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
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`define SIZE2WIDTH wbm_burst_size
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`define SIZE2WIDTH wbm_burst_size
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localparam wbm_burst_width `SIZE2WIDTH_EXPR
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localparam wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
|
`undef SIZE2WIDTH
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localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
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localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
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`define SIZE2WIDTH nr_of_wbm_burst
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`define SIZE2WIDTH nr_of_wbm_burst
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localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
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localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
|
`undef SIZE2WIDTH
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input [dw_s-1:0] wbs_dat_i;
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input [dw_s-1:0] wbs_dat_i;
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input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
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input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
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input [dw_s/8-1:0] wbs-sel_i;
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input [dw_s/8-1:0] wbs_sel_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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input wbs_we_i;
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input wbs_we_i, wbs_stb_i, wbs_cyc_i;
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output [dw_s-1:0] wbs_dat_o;
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output [dw_s-1:0] wbs_dat_o;
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output wbs_ack_o;
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output wbs_ack_o;
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input wbs_clk, wbs_rst;
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input wbs_clk, wbs_rst;
|
|
|
output [dw_m-1:0] wbm_dat_o;
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output [dw_m-1:0] wbm_dat_o;
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output [aw_m-1:0] wbm_adr_o;
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output [aw_m-1:0] wbm_adr_o;
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output [dw_m/8-1:0] wbm_sel_o;
|
output [dw_m/8-1:0] wbm_sel_o;
|
output [2:0] wbm_cti_o;
|
output [2:0] wbm_cti_o;
|
output [1:0] wbm_bte_o;
|
output [1:0] wbm_bte_o;
|
|
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
|
input [dw_m-1:0] wbm_dat_i;
|
input [dw_m-1:0] wbm_dat_i;
|
input wbm_ack_i;
|
input wbm_ack_i;
|
input wbm_stall_i;
|
input wbm_stall_i;
|
input wbm_clk, wbm_rst;
|
input wbm_clk, wbm_rst;
|
|
|
wire dirty, valid;
|
wire dirty, valid;
|
wire [aw_tag-1:0] tag;
|
wire [aw_tag-1:0] tag;
|
wire tag_mem_we;
|
wire tag_mem_we;
|
wire [aw_tag-1:0] wbs_adr_tag;
|
wire [aw_tag-1:0] wbs_adr_tag;
|
wire [aw_slot-1:0] wbs_adr_slot;
|
wire [aw_slot-1:0] wbs_adr_slot;
|
wire [aw_offset_1:0] wbs_adr_word;
|
wire [aw_offset-1:0] wbs_adr_word;
|
wire [aw-1:0] wbs_adr;
|
wire [aw_s-1:0] wbs_adr;
|
|
|
reg [1:0] state;
|
reg [1:0] state;
|
localparam idle = 2'h0;
|
localparam idle = 2'h0;
|
localparam rdwr = 2'h1;
|
localparam rdwr = 2'h1;
|
localparam push = 2'h2;
|
localparam push = 2'h2;
|
| Line 1203... |
Line 1205... |
wire eoc;
|
wire eoc;
|
|
|
// cdc
|
// cdc
|
wire done, mem_alert, mem_done;
|
wire done, mem_alert, mem_done;
|
|
|
|
// wbm side
|
|
reg [aw_m-1:0] wbm_radr;
|
|
reg [aw_m-1:0] wbm_wadr;
|
|
wire [aw_slot+-1:0] wbm_adr;
|
|
wire wbm_radr_cke, wbm_wadr_cke;
|
|
|
|
reg [1:0] phase;
|
|
localparam wbm_wait = 2'b00;
|
|
localparam wbm_rd = 2'b10;
|
|
localparam wbm_wr = 2'b11;
|
|
|
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
|
|
`define MODULE ram
|
`define MODULE ram
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .data_width(aw_tag), .addr_Width(aw_slot))
|
# ( .data_width(aw_tag), .addr_width(aw_slot))
|
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
|
tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
|
`undef MODULE
|
`undef MODULE
|
assign valid = wbs_adr_tag == tag;
|
assign valid = wbs_adr_tag == tag;
|
|
|
`define MODULE wb_adr_inc
|
`define MODULE wb_adr_inc
|
`BASE`MODULE # ( .adr_width(aw_slot+aw_offset), .max_burst_width(max_burst_width)) adr_inc0 (
|
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
|
.cyc_i(wbs_cyc_i),
|
.cyc_i(wbs_cyc_i),
|
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
|
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
|
.cti_i(wbs_cti_i),
|
.cti_i(wbs_cti_i),
|
.bte_i(wbs_bte_i),
|
.bte_i(wbs_bte_i),
|
.adr_i(wbs_adr_i),
|
.adr_i(wbs_adr_i),
|
| Line 1229... |
Line 1242... |
.rst(wbsa_rst));
|
.rst(wbsa_rst));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE dpram_be_2r2w
|
`define MODULE dpram_be_2r2w
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .data_width(aw_tag), .addr_Width(aw_slot+aw_offset))
|
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr), be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
.d_b(wbm_dat_i), .adr_b(wbm_adr), be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
.d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
case <= idle;
|
state <= idle;
|
else
|
else
|
case (state)
|
case (state)
|
idle:
|
idle:
|
if (wbs_cyc_i)
|
if (wbs_cyc_i)
|
state <= rdwr;
|
state <= rdwr;
|
| Line 1276... |
Line 1289... |
assign mem_alert = state==rdwr & !valid;
|
assign mem_alert = state==rdwr & !valid;
|
assign done = mem_done;
|
assign done = mem_done;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (rst)
|
|
wbm_burst_adr <= {aw_wbm_burst{1'b0}};
|
|
else
|
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i))
|
|
wbm_burst_adr <= wbm_burst_adr + (aw_wbm_burst)'d1
|
|
|
|
// FSM generating a number of burts 4 cycles
|
// FSM generating a number of burts 4 cycles
|
// actual number depends on data width ratio
|
// actual number depends on data width ratio
|
// nr_of_wbm_burst
|
// nr_of_wbm_burst
|
reg [wbm_burst_width-1:0] cnt0;
|
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
|
reg [nr_of_wbm_burst_width-1:0] cnt1;
|
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (wbm_rst)
|
|
cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
|
else
|
|
if (wbm_radr_cke)
|
|
cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
|
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
|
|
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
{cnt1,cnt0} <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
else
|
else
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
if (wbm_wadr_cke)
|
{cnt1,cnt0} <= (nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
|
assign wbm_wadr_cke = wbm_ack_i;
|
|
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
|
if (wbm_rst)
|
|
phase <= wbm_wait;
|
|
else
|
|
case (phase)
|
|
wbm_wait:
|
|
if (mem_alert)
|
|
phase <= state;
|
|
wbm_wr:
|
|
if (&cnt1 & wbm_ack_i)
|
|
phase <= wbm_rd;
|
|
wbm_rd:
|
|
if (&cnt0 & wbm_ack_i)
|
|
phase <= idle;
|
|
default: phase <= wbm_wait;
|
|
endcase
|
|
|
|
assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
|
|
assign wbm_adr = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
|
|
assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
|
|
assign wbm_bte_o = bte;
|
|
assign wbm_we_o = phase==wbm_wr;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
