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https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk
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reg wb_clk, wb_rst;
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reg wb_clk, wb_rst;
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reg sdram_clk, sdram_rst;
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reg sdram_clk, sdram_rst;
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reg tb_rst;
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reg tb_rst;
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wire [31:0] wb0_dat_i;
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wire [31:0] wbm_dat_i [1:nr_of_wbm];
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wire [3:0] wb0_sel_i;
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wire [3:0] wbm_sel_i [1:nr_of_wbm];
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wire [31:0] wb0_adr_i;
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wire [31:0] wbm_adr_i [1:nr_of_wbm];
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wire [2:0] wb0_cti_i;
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wire [2:0] wbm_cti_i [1:nr_of_wbm];
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wire [1:0] wb0_bte_i;
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wire [1:0] wbm_bte_i [1:nr_of_wbm];
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wire wb0_cyc_i;
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wire wbm_cyc_i [1:nr_of_wbm];
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wire wb0_stb_i;
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wire wbm_stb_i [1:nr_of_wbm];
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wire [31:0] wb0_dat_o;
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wire [31:0] wbm_dat_o [1:nr_of_wbm];
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wire wb0_ack_o;
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wire wbm_ack_o [1:nr_of_wbm];
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wire wbm_clk [1:nr_of_wbm];
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wire [31:0] wb1_dat_i;
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wire wbm_rst;
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wire [3:0] wb1_sel_i;
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wire [31:0] wb1_adr_i;
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wire [31:0] wb_sdram_dat_i;
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wire [2:0] wb1_cti_i;
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wire [3:0] wb_sdram_sel_i;
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wire [1:0] wb1_bte_i;
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wire [31:0] wb_sdram_adr_i;
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wire wb1_cyc_i;
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wire [2:0] wb_sdram_cti_i;
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wire wb1_stb_i;
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wire [1:0] wb_sdram_bte_i;
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wire [31:0] wb1_dat_o;
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wire wb_sdram_cyc_i;
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wire wb1_ack_o;
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wire wb_sdram_stb_i;
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wire [31:0] wb_sdram_dat_o;
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wire [31:0] wb4_dat_i;
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wire wb_sdram_ack_o;
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wire [3:0] wb4_sel_i;
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wire [31:0] wb4_adr_i;
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wire [2:0] wb4_cti_i;
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wire [1:0] wb4_bte_i;
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wire wb4_cyc_i;
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wire wb4_stb_i;
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wire [31:0] wb4_dat_o;
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wire wb4_ack_o;
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wire [1:0] ba, bad;
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wire [1:0] ba, bad;
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wire [12:0] a, ad;
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wire [12:0] a, ad;
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wire [15:0] dq_i;
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wire [15:0] dq_i;
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wire [15:0] dq_o;
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wire [15:0] dq_o;
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// Wishbone clock
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// Wishbone clock
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initial
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initial
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begin
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begin
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#0 wb_clk = 1'b0;
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#0 wb_clk = 1'b0;
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forever
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forever
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//#200 wb_clk = !wb_clk; // 2.5 MHz
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#(wb0_clk_period/2) wb_clk = !wb_clk;
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#20 wb_clk = !wb_clk; // 25 MHz
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end
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end
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// SDRAM clock
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// SDRAM clock
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initial
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initial
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begin
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begin
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#0 sdram_clk = 1'b0;
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#0 sdram_clk = 1'b0;
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forever
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forever
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#4 sdram_clk = !sdram_clk; // 125 MHz
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#(sdram_clk_period/2) sdram_clk = !sdram_clk;
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//#5 sdram_clk = !sdram_clk; // 100 MHz
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end
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end
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endmodule // versatile_mem_ctrl_tb
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endmodule // versatile_mem_ctrl_tb
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