| Line 58... |
Line 58... |
@cindex Introduction to this @value{DESIGN}
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@cindex Introduction to this @value{DESIGN}
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This design implements a versatile memory controller. If used in combination with the versitale library, available from OpenCores,
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This design implements a versatile memory controller. If used in combination with the versitale library, available from OpenCores,
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different types of system can easily be designed, including use cases where the system bus is in one clock domain and the memory
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different types of system can easily be designed, including use cases where the system bus is in one clock domain and the memory
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controller in an other.
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controller in an other.
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@section Dependencies to other IP cores
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This design uses the following IP coreas available from OpenCores project verstile library.
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@itemize @bullet
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@item vl_cnt_shreg_ce_clear
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@item vl_dff_ce_clear
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@item vl_cnt_lfsr_zq
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@item vl_dff
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@item vl_o_dff
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@item vl_io_dff_oe
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@end itemize
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@node Block diagram
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@node Block diagram
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@chapter Block Diagram
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@chapter Block Diagram
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@cindex Block diagram
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@cindex Block diagram
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@section Clock domains
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@section Synchronous design
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@value{DESIGN} contains the following clock domains
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@image{block-sdram}
|
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Synchronous design where wishbone clock domain is equal to SDRAM and SDRAM controller clock domain.
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@section Asynchronous design
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@image{block-sdram-wbwb}
|
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Asynchronous design where wishbone and SDRAM clock domain are independant. A wishbone rev B3 compatilble bridge
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is available in project versatile_library from OpenCores, http://www.opencores.org.
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|
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@section Asynchronous design with multiple wishbone interfaces
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@image{block-sdram-wbwb-arbiter}
|
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Asynchronous design where wishbone and SDRAM clock domain are independant. Multiple wishbone port with use of a wishbone arbiter.
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@node SDR SDRAM controller
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@chapter SDR SDRAM controller
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@section Module defines
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@multitable @columnfractions .2 .8
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@headitem Name @tab Description
|
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@item NO_BURST @tab Define if burst cycles not used
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@item WRAP4 @tab Define to support 4 word wrap burst
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@item WRAP8 @tab Define to support 8 word wrap burst
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@item WRAP16 @tab Define to support 16 word wrap burst
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@end multitable
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@section Module parameters
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@multitable @columnfractions .2 .1 .7
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@headitem Name @tab Default value @tab Description
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@item ba_size @tab 2 @tab Bank adress vector size
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@item row_size @tab 13 @tab Row adress vector size
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@item col_size @tab 9 @tab Column adress vector size
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@item cl @tab 2 @tab CAS latency
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@end multitable
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|
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Parameters ba_size, col_size and row_size should be set depending on memory configuration. The following
|
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table holds figures for some SDRAM memories.
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@multitable @columnfractions .15 .25 .1 .1 .1 .3
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@headitem Manufacturer @tab Partnumber @tab ba_size @tab row_size @tab col_size @tab Memory size
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@item Micron @tab MT48LC4M16 @tab 2 @tab 12 @tab 8 @tab 8Mbyte
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@item Micron @tab MT48LC8M16 @tab 2 @tab 12 @tab 9 @tab 16Mbyte
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@item Micron @tab MT48LC16M16 @tab 2 @tab 13 @tab 9 @tab 32Mbyte
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@item Micron @tab MT48LC32M16 @tab 2 @tab 13 @tab 10 @tab 64Mbyte
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@end multitable
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|
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Parameter cl should be set to either 2 or 3 depending on SDRAM clock.
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|
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@section Module IO signals
|
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@subsection Wishbone signals
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@multitable @columnfractions .2 .1 .1 .6
|
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@headitem Name @tab Dir @tab Width @tab Description
|
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@item dat_i @tab I @tab 32 @tab Input data vector
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@item adr_i @tab I @tab @tab Adress vector
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@item sel_i @tab I @tab 4 @tab Byte select signals
|
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@item bte_i @tab I @tab 2 @tab Bus tag identifier
|
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@item we_i @tab I @tab 1 @tab Write enable
|
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@item cyc_i @tab I @tab 1 @tab Active cycle indicator
|
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@item stb_i @tab I @tab 1 @tab Strobe
|
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@item dat_o @tab O @tab 32 @tab Output data vector
|
|
@item ack_o @tab O @tab 1 @tab Acknowledge signal
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@end multitable
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|
|
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Wishbone signal bte_i is optional and is only used for designs supporting burst transfer.
|
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@subsection SDRAM signals
|
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@multitable @columnfractions .2 .1 .1 .6
|
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@headitem Name @tab Dir @tab Width @tab Description
|
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@item ba @tab O @tab ba_size @tab Bank adress vector
|
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@item a @tab O @tab 13 @tab Adress vector
|
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@item cmd @tab O @tab 3 @tab SDRAM command, {ras_n, cas_n, we_n}
|
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@item cke @tab O @tab 1 @tab Clock enable
|
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@item cs_n @tab O @tab 1 @tab Chip select, active low
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@item dqm @tab O @tab 2 @tab Data mask
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@item dq_i @tab I @tab 16 @tab Data input vector
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@item dq_o @tab O @tab 16 @tab Data output vector
|
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@item dq_oe @tab O @tab 1 @tab Data output enable
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@end multitable
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@subsection System signals
|
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@multitable @columnfractions .2 .1 .1 .6
|
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@headitem Name @tab Dir @tab Width @tab Description
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@item clk @tab I @tab 1 @tab SDRAM system clock
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@item rst @tab I @tab 1 @tab Asynchronous reset, active hig
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@end multitable
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@node SDR SDRAM 16 bit data bus controller
|
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@chapter SDR SDRAM 16 bit data bus controller
|
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@cindex SDR SDRAM 16 bit data bus controller
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@section State machine implementation
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|
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Design is based on a state machine as described below.
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|
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@image{sdr_sdram_16,14cm,16cm,,.png}
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|
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A counter is incremented on each cycle the state machine reside in any given state.
|
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When changing state a counter clear is issued. The counter state vector is used for
|
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two things
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@itemize
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@itemize
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@item Wishbone slave clock domain
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@item controlling outputs, ie defining cmd and other control signals
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@item Wishbone master clock domain
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@item to make sure timing reqiurements are fulfilled, ie define time from precharge to activate
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@item RX GMII clock domain
|
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@item TX GMII clock domain
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@end itemize
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@end itemize
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@node Configuration registers
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@subsection State - init
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@chapter Configuration registers
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|
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@section Register memory map
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The init state is responsible to make sure that a proper start-up and initialization of the SDRAM is
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@multitable @columnfractions .2 .1 .1 .1 .5
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performed. The following sequence should be applied:
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@headitem Name @tab Address @tab Width @tab Access @tab Description
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@enumerate
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@item MODER @tab @value{MODER} @tab 32 @tab RW @tab Mode register
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@item assert CKE low
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@item INT_SOURCE @tab @value{INT_SOURCE} @tab 32 @tab RW @tab Interrupt source register
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@item provide stable clock
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@item INT_MASK @tab @value{INT_MASK} @tab 32 @tab RW @tab Interrupt mask register
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@item bring CKE high
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@item TX_BD_NUM @tab @value{TX_BD_NUM} @tab 32 @tab RW @tab Transmit Buffer Descriptor number
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@item perform PRECHARGE ALL command and wait for tRP
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@item MIIMODER @tab @value{MIIMODER} @tab 32 @tab RW @tab MII Mode Register
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@item issue AUTO RERFESH and wait for tRFC
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@item MIICOMMAND @tab @value{MIICOMMAND} @tab 32 @tab RW @tab MII Command Register
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@item issue AUTO RERFESH and wait for tRFC
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@item MIIADDRESS @tab @value{MIIADDRESS} @tab 32 @tab RW @tab MII Address Register
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@item LOAD MODE REGISTER and wait for tMR
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@item MIITX_DATA @tab @value{MIITX_DATA} @tab 32 @tab RW @tab MII Transmit Data
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@end enumerate
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@item MIIRX_DATA @tab @value{MIIRX_DATA} @tab 32 @tab RW @tab MII Receive Data
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After this state machine advances to idle state
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@item MIISTATUS @tab @value{MIISTATUS} @tab 32 @tab RW @tab MII Status Register
|
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@item MAC_ADDR0 @tab @value{MAC_ADDR0} @tab 32 @tab RW @tab MAC address, LSB four bytes
|
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@item MAC_ADDR1 @tab @value{MAC_ADDR1} @tab 32 @tab RW @tab MAC address, MSB two bytes
|
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@end multitable
|
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|
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@page
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@subsection State - idle
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@subsection MODER
|
In state idle implementation awaits two different condition, appearing in order of priority
|
@multitable @columnfractions .1 .1 .2 .6
|
@enumerate
|
@headitem Bit @tab Access @tab Description @tab
|
@item refresh request => next state is rfr
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@item 31-17 @tab @tab Reserved
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@item cyc_i & stb_i => next state is adr
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@item 16 @tab RW @tab RECSMALL @tab Receive small packets
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@end enumerate
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@item 15 @tab RW @tab PAD @tab Padding enabled
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@item 14 @tab RW @tab HUGEN @tab Huge Packets Enable
|
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@item 13 @tab RW @tab CRCEN @tab CRC enable
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@item 12-8 @tab @tab Reserved
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@item 7 @tab RW @tab LOOPBCK @tab Loopback
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@item 6 @tab RW @tab Resrved
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@item 5 @tab RW @tab PRO @tab Promiscuous
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@item 4 @tab @tab Reserved
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@item 3 @tab RW @tab BRO @tab Broadcast Address
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@item 2 @tab @tab Reserved
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@item 1 @tab RW @tab TXEN @tab Transmit Enable
|
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@item 0 @tab RW @tab RXEN @tab Receive Enable
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@end multitable
|
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@example
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Reset value:
|
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MODER: 0x0000A000
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@end example
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@page
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@subsection INT_SOURCE
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@multitable @columnfractions .1 .1 .2 .6
|
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@headitem Bit @tab Access @tab Description @tab
|
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@item 31-7 @tab @tab Reserved
|
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@item 4 @tab RW @tab BUSY @tab Busy@* This bit indicates that a buffer was received and discarded due to a lack of buffers. It is cleared by writing 1 to it. This bit appears regardless to the IRQ bits in the Receive or Transmit Buffer Descriptors.
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@item 3 @tab RW @tab RXE @tab Receive error@* This bit indicates that an error occurred while receiving data. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor.
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@item 2 @tab RW @tab RXB @tab Receive buffer@* This bit indicates that a frame was received. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor. If a control frame is received, then RXC bit is set instead of the RXB bit.
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@item 1 @tab RW @tab TXE @tab Transmit error@* This bit indicates that a buffer was not transmitted due to a transmit error. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Receive Buffer Descriptor. This bit appears only when IRQ bit is set in the Transmit Buffer Descriptor.
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@item 0 @tab RW @tab TXB @tab Transmit buffer@* This bit indicates that a buffer has been transmitted. It is cleared by writing 1 to it. This bit appears only when IRQ bit is set in the Transmit Buffer Descriptor.
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@end multitable
|
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@example
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Reset value:
|
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INT_SOURCE: 0x00000000
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@end example
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@page
|
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@subsection INT_MASK
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@multitable @columnfractions .1 .1 .2 .6
|
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@headitem Bit @tab Access @tab Description @tab
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@item 31-7 @tab @tab Reserved
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@item 4 @tab RW @tab BUSY_M @tab Busy mask@*
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@item 3 @tab RW @tab RXE_M @tab Receive error@* Receive error mask
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@item 2 @tab RW @tab RXB_M @tab Receive buffer@* Receive buffer mask
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@item 1 @tab RW @tab TXE_M @tab Transmit error@* Transmit error mask
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@item 0 @tab RW @tab TXB_M @tab Transmit buffer@* Transmit buffer mask
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@end multitable
|
|
@example
|
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Reset value:
|
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INT_MASK: 0x00000000
|
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@*@*
|
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0 -> event masked
|
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1 -> event causes an interrupt
|
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@end example
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@page
|
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@subsection TX_BD_NUM
|
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@multitable @columnfractions .1 .1 .2 .6
|
|
@headitem Bit @tab Access @tab Description @tab
|
|
@item 31-8 @tab @tab Reserved
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@item 7-0 @tab RW @tab TX_BD_NUM @tab Transmit Buffer Descriptor Number@* Number of the Tx BD. Number of the Rx BD equals to the (0x80 – Tx BD number). Maximum number of the Tx BD is 0x80. Values greater then 0x80 cannot be written to this register (ignored).
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@end multitable
|
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@example
|
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Reset value:
|
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TX_BD_NUM: 0x00000040
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@end example
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@page
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@subsection MIIMODER
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@multitable @columnfractions .1 .1 .2 .6
|
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@headitem Bit @tab Access @tab Description @tab
|
|
@item 31-9 @tab @tab Reserved
|
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@item 8 @tab RW @tab MIINOPRE @tab No Preamble@* 0 = 32 bit preamble sent@* 1 = No preamble sent
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@item 7-0 @tab RW @tab CLKDIV @tab Clock divider The field is a host clock divider factor. The host clock can be divided by an even number, greater then 1. The default value is 0x64 (100).
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@end multitable
|
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@example
|
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Reset value:
|
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MIIMODER: 0x00000064
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@end example
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@subsection MIICOMMAND
|
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@multitable @columnfractions .1 .1 .2 .6
|
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@headitem Bit @tab Access @tab Description @tab
|
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@item 31-3 @tab @tab Reserved
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@item 2 @tab RW @tab WCTRLDATA @tab Write control data
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@item 1 @tab RW @tab RSTAT @tab Read status
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@item 0 @tab RW @tab SCANSTAT @tab Scan status
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@end multitable
|
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@example
|
|
Reset value:
|
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MIICOMMAND: 0x00000000
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@end example
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@subsection MIIADDRESS
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@multitable @columnfractions .1 .1 .2 .6
|
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@headitem Bit @tab Access @tab Description @tab
|
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@item 31-13 @tab @tab Reserved
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@item 12-8 @tab RW @tab RGAD @tab Register address
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@item 7-5 @tab RW @tab Reserved @tab
|
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@item 4-0 @tab RW @tab FIAD @tab PHY address
|
|
@end multitable
|
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@example
|
|
Reset value:
|
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MIIADDRESS: 0x00000000
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@end example
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|
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@subsection MIITX_DATA
|
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@multitable @columnfractions .1 .1 .2 .6
|
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@headitem Bit @tab Access @tab Description @tab
|
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@item 31-16 @tab @tab Reserved
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@item 15-0 @tab RW @tab CTRLDATA @tab Data to be written to the PHY
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@end multitable
|
|
@example
|
|
Reset value:
|
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MIITX_DATA: 0x00000000
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@end example
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|
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@subsection MIIRX_DATA
|
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@multitable @columnfractions .1 .1 .2 .6
|
|
@headitem Bit @tab Access @tab Description @tab
|
|
@item 31-16 @tab @tab Reserved
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@item 15-0 @tab R @tab PRSD @tab Data read from the PHY
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@end multitable
|
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@example
|
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Reset value:
|
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MIIRX_DATA: 0x00000000
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@end example
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@subsection MIISTATUS
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@multitable @columnfractions .1 .1 .2 .6
|
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@headitem Bit @tab Access @tab Description @tab
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@item 31-3 @tab @tab Reserved
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@item 2 @tab R @tab NVALID @tab Invalid@* 0 = The data in the MSTATUS register is valid.@* 1 = The data in the MSTATUS register is invalid.@* This bit is only valid when the scan status operation is active.
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@item 1 @tab R @tab BUSY @tab 0 = The MII is ready.@* 1 = The MII is busy (operation in progress).
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@item 0 @tab R @tab LINKFAIL @tab 0 = The link is OK.@*1 = The link failed.@*The Link fail condition occurred (now the link might be OK). Another status read gets a new status.
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@end multitable
|
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@example
|
|
Reset value:
|
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MIISTATUS: 0x00000000
|
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@end example
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|
|
@page
|
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@subsection MAC_ADDR0
|
|
@multitable @columnfractions .1 .1 .8
|
|
@headitem Bit @tab Access @tab Description @tab
|
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@item 31-24 @tab RW @tab Byte 2 of the Ethernet MAC address
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@item 23-16 @tab RW @tab Byte 3 of the Ethernet MAC address
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@item 15-8 @tab RW @tab Byte 4 of the Ethernet MAC address
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@item 7-0 @tab RW @tab Byte 5 of the Ethernet MAC address
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|
@end multitable
|
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@example
|
|
Reset value:
|
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MAC_ADDR0: 0x00000000
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@end example
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|
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@subsection MAC_ADDR1
|
|
@multitable @columnfractions .1 .1 .8
|
|
@headitem Bit @tab Access @tab Description @tab
|
|
@item 31-16 @tab @tab Reserved
|
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@item 15-8 @tab RW @tab Byte 0 of the Ethernet MAC address
|
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@item 7-0 @tab RW @tab Byte 1 of the Ethernet MAC address
|
|
@end multitable
|
|
@example
|
|
Reset value:
|
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MAC_ADDR1: 0x00000000
|
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@end example
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|
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@node MDIO
|
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@chapter Management Data Input/Output
|
|
|
|
The MDIO interface is implemented by two lines:
|
@subsection State - adr
|
@itemize
|
|
@item a MDC clock line
|
Depending on status of open bank and open rows choice is taken whether to precharge and activate, activate or go
|
@item an MDIO data line
|
directly to read write state. Reason for this as a separate state is to be able to have comparison result as a
|
@end itemize
|
registered signal to achive an higher clock frequency.
|
|
|
|
@subsection State - pch
|
|
|
|
Open row in current bank is deactivated. State machine waits in pch state to fulfill tRP.
|
|
|
|
@subsection State - act
|
|
|
|
Row in current bank is activated. State machine waits in act state to fulfill tRCD.
|
|
|
|
@subsection State - rw
|
|
|
|
A two word read or write burst is started. If wishbone cycle is of type burst column will get incremented
|
|
with possible wrap around and a new burst started for each 32 bit word.
|
|
|
|
@section Timing
|
|
|
|
The follwoing timing requirements must be fulfilled:
|
|
|
The clock line is driven by the MAC device. The data line is bidirectional: the PHY drives it to provide register data at the end of a read operation.
|
|
@*@*
|
|
The bus has a single MAC master, but can have up to 32 PHY slaves.
|
|
@*@*
|
|
The MDC clock can be aperiodic, with a minimum period of 400 ns, which corresponds to a maximal frequency of 2.5 MHz. Newer chips, however, allow faster acesses.
|
|
@*@*
|
|
The MDIO data line has a pull-up of 1.5 kOhm in the PHY, allowing the MAC to determine if one or more PHYs are attached. The MAC should have a 2 kOhm pull-down on that same line.
|
|
|
|
@section Bus timing
|
|
@subsection Read operation
|
|
A read operation has the following phases
|
|
@itemize
|
@itemize
|
@item Preamble with 32 ones
|
@item tMR - Load Mode Register period
|
@item Start sequence, 01
|
@item tRCD - Active to read/write delay
|
@item Opcode read, 10
|
@item tRP - Precharge command period
|
@item PHY adress
|
@item tRFC - Auto refresh period
|
@item REG adress
|
@item tREF - refresh period
|
@item Bus turnaround
|
|
@item Register data
|
|
@end itemize
|
@end itemize
|
@image{MDIO_rd,15cm,2.54cm}
|
|
|
|
@subsection Write operation
|
In the SDRAM datasheet the above timing figures will be given in ns and should be
|
A write operation has the following phases
|
converted to number of clock cycles. All of the above timing figures, except tREF, are implemented as parameters
|
|
in the design and should be set depending on SDRAM figures and actual clock period. All
|
|
parameters have default values of 2 clock cycles.
|
|
|
|
@subsection Bank/Row activation - tRCD
|
|
|
|
@image{tRCD,15cm,5cm,,.png}
|
|
|
|
Minimum time between activation of and read or write command.
|
|
@subsection Auto refresh mode
|
|
|
|
@image{aref,15cm,15cm,,.png}
|
|
|
|
Minumum time between precharge and auto refresh and active command.
|
|
|
|
@subsection Refresh period - tREF
|
|
|
|
The auto refresh period, tREF must be met. During auto refresh an internal address counter
|
|
is used and adress signals are treated as don't care. During the refresh period each row must
|
|
be refreshed. @*
|
|
For example consider a SDRAM with tREF = 64 ms and row size of 8K. An auto refresh command
|
|
should be issued once every 64 ms / 8192 = 7.813 us.@*
|
|
The refresh interval counter is implemented as an LFSR style counter for minimal area and maximum
|
|
performance. To accurately set the wrap value for this counter use the application VersatileCounter found
|
|
in the versatile library project at opencores. This program gives the wrap value for a given vector length.
|
|
Assuming an SDRAM clock frequency of 133 MHz which equals a period time of 7.5 ns we should issue an auto
|
|
refresh every 7.813 us / 7.5 ns = 1041 cycle. We need a state vector of 11 bits in the counter.@*
|
|
To get the wrap value we use the application@*
|
|
@command{./VersatileCounter.php 11 1041@*11111110101}
|
|
|
|
@node Example: Timing setup
|
|
@chapter Example: Timing setup
|
|
|
|
@section Requirements
|
|
|
|
SDRAM device to use:
|
@itemize
|
@itemize
|
@item Preamble with 32 ones
|
@item Micron MT48LC32M16-7E
|
@item Start sequence, 01
|
|
@item Opcode read, 01
|
|
@item PHY adress
|
|
@item REG adress
|
|
@item Bus turnaround
|
|
@item Register data
|
|
@end itemize
|
@end itemize
|
@image{MDIO_wr,15cm,2.54cm}
|
|
|
|
@node Ingress and Egress FIFO
|
@multitable @columnfractions .4 .2 .1 .1 .1 .1
|
@chapter Ingress and Egress FIFO
|
@headitem Parameter @tab Symbol @tab Min @tab Max @tab Unit
|
|
@item Auto refresh period @tab tRFC @tab 66 @tab - @tab ns
|
|
@item Precharge command period @tab tRP @tab 15 @tab - @tab ns
|
|
@item Active to read or write delay @tab tRCD @tab 15 @tab - @tab ns
|
|
@item Load mode register command to active or refresh @tab tMRD @tab 2 @tab - @tab tCK
|
|
@item Refresh periods (8192 rows) @tab tREF @tab 66 @tab -@tab ms
|
|
@end multitable
|
|
|
|
Intended operating frequency is 75 MHz, tCK = 13.333 ns
|
|
|
|
@section Parameter settings
|
|
|
|
@multitable @columnfractions .2 .8
|
|
@headitem Symbol @tab Value
|
|
@item tRFC @tab 5
|
|
@item tRP @tab 2
|
|
@item tRCD @tab 2
|
|
@item tMRD @tab 2
|
|
@end multitable
|
|
@*
|
|
Refresh rate is 66 ms / 8192 = 8.057 us@*
|
|
Number of clock cycles between refresh request 8.057 us / 13.333 ns = 604@*
|
|
@*
|
|
To get the wrap value we use the application from Versatile Library@*
|
|
@command{./VersatileCounter.php 10 604@*0101001110}
|
|
|
@section FIFO implementation
|
|
Both ingress and egress FIFO implementation uses a generic asynchronous FIFO design
|
|
available from OpenCores.@*@*
|
|
@uref{http://opencores.org/project,versatile_library}
|
|
|
|
@c ****************************************************************************
|
@c ****************************************************************************
|
@c End bits
|
@c End bits
|
@c ****************************************************************************
|
@c ****************************************************************************
|
|
|
