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---- VHDL Wishbone TESTBENCH ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- ----
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---- This file contains the highest (top) module of the test ----
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---- This file contains constants for the test bench, such as ----
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---- bench. ----
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---- register definitions. ----
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---- It instantiates the design under test (DUT), instantiates ----
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---- the stimulator module for test vector generation, ----
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---- instantiates the verifier module for result comparison, ----
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---- instantiates the test case top (testcase_top) bfm, ----
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---- interconnects all three components, generates DUT-external ----
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---- clocks and resets. ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - Sinx, email@opencores.org ----
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---- - Sinx, sinx@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- SVN information
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---- SVN information
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--
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----
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-- $URL: $
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---- $URL: $
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-- $Revision: $
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---- $Revision: $
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-- $Date: $
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---- $Date: $
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-- $Author: $
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---- $Author: $
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-- $Id: $
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---- $Id: $
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--
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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constant verifier_register0_c : integer := verifier_base_c + 16#0000_0000#;
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constant verifier_register0_c : integer := verifier_base_c + 16#0000_0000#;
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constant verifier_register1_c : integer := verifier_base_c + 16#0000_0004#;
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constant verifier_register1_c : integer := verifier_base_c + 16#0000_0004#;
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constant verifier_register2_c : integer := verifier_base_c + 16#0000_0008#;
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constant verifier_register2_c : integer := verifier_base_c + 16#0000_0008#;
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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end package;
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end package;
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--============================================================================
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-- end of file
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--============================================================================
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No newline at end of file
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----------------------------------------------------------------------
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---- end of file ----
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----------------------------------------------------------------------
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No newline at end of file
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