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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [tb_pkg.vhd] - Diff between revs 2 and 4

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----  VHDL Wishbone TESTBENCH                                     ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----                                                              ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----                                                              ---- 
----                                                              ---- 
----  This file contains the highest (top) module of the test     ----
----  This file contains constants for the test bench, such as    ----
----  bench.                                                      ---- 
----  register definitions.                                       ---- 
----  It instantiates the design under test (DUT), instantiates   ----
 
----  the stimulator module for test vector generation,           ----
 
----  instantiates the verifier module for result comparison,     ----
 
----  instantiates the test case top (testcase_top) bfm,          ----
 
----  interconnects all three components, generates DUT-external  ----
 
----  clocks and resets.                                          ----
 
----                                                              ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----   -                                                          ---- 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - Sinx, email@opencores.org                             ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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  constant verifier_register0_c              : integer := verifier_base_c + 16#0000_0000#;
  constant verifier_register0_c              : integer := verifier_base_c + 16#0000_0000#;
  constant verifier_register1_c              : integer := verifier_base_c + 16#0000_0004#;
  constant verifier_register1_c              : integer := verifier_base_c + 16#0000_0004#;
  constant verifier_register2_c              : integer := verifier_base_c + 16#0000_0008#;
  constant verifier_register2_c              : integer := verifier_base_c + 16#0000_0008#;
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end package;
end package;
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-- end of file
 
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---- end of file                                                  ---- 
 
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