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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [tb_top.vhd] - Diff between revs 2 and 4

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---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----                                                              ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----  https://opencores.org/project/vhdl_wb_tb                    ---- 
 
----                                                              ---- 
 
----  This file contains the highest (top) module for simulation. ----
 
----  Like tb_top it instantiates the core_top module and         ----
 
----  provides parameters/generics. Where the top module provides ---- 
 
----  parameters for synthesis this file provides parameters for  ----
 
----  simulation.                                                 ----
----                                                              ---- 
----                                                              ---- 
----  This file contains the highest (top) module of the test     ----
 
----  bench.                                                      ---- 
 
----  It instantiates the design under test (DUT), instantiates   ----
----  It instantiates the design under test (DUT), instantiates   ----
----  the stimulator module for test vector generation,           ----
----  the stimulator module for test vector generation,           ----
----  instantiates the verifier module for result comparison,     ----
----  instantiates the verifier module for result comparison,     ----
----  instantiates the test case top (testcase_top) bfm,          ----
----  instantiates the test case top (testcase_top) bfm,          ----
----  interconnects all three components, generates DUT-external  ----
----  interconnects all three components, generates DUT-external  ----
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----                                                              ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----   -                                                          ---- 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - Sinx, email@opencores.org                             ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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entity tb_top is
entity tb_top is
  -- empty entity, since this is the simulation top and all test cases are defined
  -- empty entity, since this is the simulation top and all test cases are defined
  -- in the tc_xxx files.
  -- in the tc_xxx files.
end entity tb_top;
end entity tb_top;
 
 
--=architecture===============================================================
-- architecture ------------------------------------------------------
architecture rtl of tb_top is
architecture rtl of tb_top is
  --============================================================================
  -----------------------------------------------------------------------------
  constant  g_wb_clock_period               : time     := 20.0 ns;   -- 50 mhz
  constant  g_wb_clock_period               : time     := 20.0 ns;   -- 50 mhz
  --============================================================================
 
  -- signal declaration
 
  --============================================================================
 
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  signal s_wb_bfm_out                 : wishbone_bfm_master_out_t; -- from testcase_top
  signal s_wb_bfm_out                 : wishbone_bfm_master_out_t; -- from testcase_top
  signal s_wb_bfm_in                  : wishbone_bfm_master_in_t;  -- to testcase_top
  signal s_wb_bfm_in                  : wishbone_bfm_master_in_t;  -- to testcase_top
 
 
  signal s_wb_master_out              : wishbone_master_out_t;    -- from wb_decoder
  signal s_wb_master_out              : wishbone_master_out_t;    -- from wb_decoder
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  constant number_of_stimulus_signals_c : integer := 8;
  constant number_of_stimulus_signals_c : integer := 8;
  constant number_of_verify_signals_c   : integer := 8;
  constant number_of_verify_signals_c   : integer := 8;
  signal s_stimulus                   : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
  signal s_stimulus                   : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
  signal s_verify                     : std_logic_vector(number_of_verify_signals_c-1 downto 0);
  signal s_verify                     : std_logic_vector(number_of_verify_signals_c-1 downto 0);
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- other signals
 
 
 
  -----------------------------------------------------------------------------
 
begin
begin
  --============================================================================
  -----------------------------------------------------------------------------
  --clocks---------------------------------------------------------------------
  --clocks---------------------------------------------------------------------
  wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
  wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
  begin
  begin
    s_wb_clock        <= '0';
    s_wb_clock        <= '0';
    wait for g_wb_clock_period/2;
    wait for g_wb_clock_period/2;
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    end if;
    end if;
  end process;
  end process;
  s_wb_reset   <= s_wb_reset_p2;
  s_wb_reset   <= s_wb_reset_p2;
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  -- instance of test case "player"; runs tc_xxxx modules
  -- instance of test case "player"; runs tc_xxxx modules
  testcase_top_inst : entity work.testcase_top
  tc_top_inst : entity work.tc_top
    port map (
    port map (
      wb_o                => s_wb_bfm_out,
      wb_o                => s_wb_bfm_out,
      wb_i                => s_wb_bfm_in
      wb_i                => s_wb_bfm_in
      );
      );
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
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      wb_o                                => s_wb_slaves_out(1),
      wb_o                                => s_wb_slaves_out(1),
      signals_i                           => s_verify
      signals_i                           => s_verify
      );
      );
  -----------------------------------------------------------------------------
  -----------------------------------------------------------------------------
  end rtl;
  end rtl;
--============================================================================
 
-- end of file
 
--============================================================================
 
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----------------------------------------------------------------------
 
---- end of file                                                  ---- 
 
----------------------------------------------------------------------
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