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Rev 2 Rev 4
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---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----                                                              ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----                                                              ---- 
----                                                              ---- 
----  This file contains the top functional module of the design  ----
----  This file contains the verifier module which monitors the   ----
----  under test. The top functional module will be enclosed by   ----
----  DUTs responses. It is controlled via a wishbone interface   ----
----  the top module for synthesis or the tb_top for simulation.  ---- 
----  by the tc_xxxx files.                                       ---- 
----  The top module can contain some synthesis specific code,    ----
----  It can check the signals by itself or forward information   ----
----  where the tb_top contains simulation specific code.          ----
----  To the tc_xxxx files.                                       ----
----                                                              ---- 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----   -                                                          ---- 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - Sinx, email@opencores.org               ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
---- restriction provided that this copyright statement is not    ---- 
---- restriction provided that this copyright statement is not    ---- 
---- removed from the file and that any derivative work contains  ---- 
---- removed from the file and that any derivative work contains  ---- 
---- the original copyright notice and the associated disclaimer. ---- 
---- the original copyright notice and the associated disclaimer. ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file is free software; you can redistribute it   ---- 
---- This source file is free software; you can redistribute it   ---- 
---- and/or modify it under the terms of the GNU Lesser General   ---- 
---- and/or modify it under the terms of the GNU Lesser General   ---- 
---- Public License as published by the Free Software Foundation; ---- 
---- Public License as published by the Free Software Foundation; ---- 
---- either version 2.1 of the License, or (at your option) any   ---- 
---- either version 2.1 of the License, or (at your option) any   ---- 
---- later version.                                               ---- 
---- later version.                                               ---- 
----                                                              ---- 
----                                                              ---- 
---- This source is distributed in the hope that it will be       ---- 
---- This source is distributed in the hope that it will be       ---- 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
---- details.                                                     ---- 
---- details.                                                     ---- 
----                                                              ---- 
----                                                              ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
 
 
-- library -----------------------------------------------------------
-- library -----------------------------------------------------------
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
library work;
library work;
use work.convert_pkg.all;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
use work.wishbone_pkg.all;
use work.my_project_pkg.all;
use work.my_project_pkg.all;
use work.wishbone_bfm_pkg.all;
use work.wishbone_bfm_pkg.all;
 
 
-- entity ------------------------------------------------------------
-- entity ------------------------------------------------------------
entity verifier is
entity verifier is
  generic(
  generic(
    g_number_of_signals             : natural := 1
    g_number_of_signals             : natural := 1
    );
    );
  port(
  port(
    wb_i                            : in wishbone_slave_in_t;
    wb_i                            : in wishbone_slave_in_t;
    wb_o                            : out wishbone_slave_out_t;
    wb_o                            : out wishbone_slave_out_t;
 
 
    signals_i                       : in std_logic_vector(g_number_of_signals-1 downto 0)
    signals_i                       : in std_logic_vector(g_number_of_signals-1 downto 0)
    );
    );
end verifier;
end verifier;
 
 
--=architecture===============================================================
-- architecture ----------------------------------------------------------------
architecture rtl of verifier is
architecture rtl of verifier is
  --============================================================================
  ------------------------------------------------------------------------------
  -- signal declaration
  -- signal declaration
  --============================================================================
  ------------------------------------------------------------------------------
  signal  s_register0                    : std_logic_vector(31 downto 0);
  signal  s_register0                    : std_logic_vector(31 downto 0);
  signal  s_register1                    : std_logic_vector(31 downto 0);
  signal  s_register1                    : std_logic_vector(31 downto 0);
  --============================================================================
  ------------------------------------------------------------------------------
begin
begin
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  wb_o.ack <= '1';
  wb_o.ack <= '1';
  wb_o.err <= '0';
  wb_o.err <= '0';
  wb_o.rty <= '0';
  wb_o.rty <= '0';
  wb_o.int <= '0';
  wb_o.int <= '0';
  wb_o.tgd <= (others => '0');
  wb_o.tgd <= (others => '0');
 
 
  -- read data multiplexer
  -- read data multiplexer
  proc_read_data_mux : process (all)
  proc_read_data_mux : process (all)
    begin
    begin
      case wb_i.adr(27 downto 0) is
      case wb_i.adr(27 downto 0) is
        when 28X"000_0000" =>
        when 28X"000_0000" =>
          wb_o.dat <= s_register0;
          wb_o.dat <= s_register0;
        when 28X"000_0004" =>
        when 28X"000_0004" =>
          wb_o.dat <= s_register1;
          wb_o.dat <= s_register1;
        when 28X"000_0008" =>
        when 28X"000_0008" =>
          wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
          wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
        when others =>
        when others =>
          wb_o.dat <= (others =>'U');
          wb_o.dat <= (others =>'U');
      end case;
      end case;
    end process;
    end process;
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  -- write signals to control the verifier
  -- write signals to control the verifier
  proc_avalon_write_data  : process (all)
  proc_avalon_write_data  : process (all)
    begin
    begin
      if (wb_i.rst = '1') then
      if (wb_i.rst = '1') then
        s_register0        <= (others => '0');
        s_register0        <= (others => '0');
        s_register1        <= (others => '0');
        s_register1        <= (others => '0');
      elsif (rising_edge(wb_i.clk)) then
      elsif (rising_edge(wb_i.clk)) then
        if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
        if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
          case wb_i.adr(27 downto 0) is
          case wb_i.adr(27 downto 0) is
            when 28X"000_0000" =>
            when 28X"000_0000" =>
              s_register0        <= wb_i.dat;
              s_register0        <= wb_i.dat;
            when 28X"000_0004" =>
            when 28X"000_0004" =>
              s_register1        <= wb_i.dat;
              s_register1        <= wb_i.dat;
            when others =>
            when others =>
          end case;
          end case;
        end if;
        end if;
      end if;
      end if;
    end process;
    end process;
 
 
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
--============================================================================
 
end rtl; --verifier
end rtl; --verifier
--============================================================================
 
-- end of file
 
--============================================================================
 
 
 
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