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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [wishbone_bfm_pkg.vhd] - Diff between revs 20 and 23

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Line 16... Line 16...
----                                                              ---- 
----                                                              ---- 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----    SVN information
----    SVN information
----
----
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $
---- $Revision: 20 $
---- $Revision: 23 $
----     $Date: 2018-08-01 11:58:41 +0200 (Wed, 01 Aug 2018) $
----     $Date: 2018-08-01 12:40:03 +0200 (Wed, 01 Aug 2018) $
----   $Author: sinx $
----   $Author: sinx $
----       $Id: wishbone_bfm_pkg.vhd 20 2018-08-01 09:58:41Z sinx $
----       $Id: wishbone_bfm_pkg.vhd 23 2018-08-01 10:40:03Z sinx $
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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  procedure wb_write(
  procedure wb_write(
    address_i                  : in  integer; -- address to write to
    address_i                  : in  integer; -- address to write to
    data_i                     : in  integer; -- data value to be written
    data_i                     : in  integer; -- data value to be written
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- incoming wb signals
    display_error_message_i    : in  integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing
    verbose_mode_i              : in  integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing
    additional_error_message_i : in  string  := "" -- string to be added in front of generated message
    message_prolog_i            : in  string  := "" -- string to be added in front of generated message
    );
    );
 
 
  -- generate single read cycle and verify read word with expected_data_i
  -- generate single read cycle and verify read word with expected_data_i
  procedure wb_read(
  procedure wb_read(
    address_i                  : in  integer; -- address to read from
    address_i                  : in  integer; -- address to read from
    expected_data_i            : in  integer; -- data to be compared to read data; if different an error message is generated
    expected_data_i            : in  integer; -- data to be compared to read data; if different an error message is generated
    signal i                   : in  wishbone_bfm_master_in_t;  -- incoming wb signals
    signal i                   : in  wishbone_bfm_master_in_t;  -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    display_error_message_i    : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
    verbose_mode_i              : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
    additional_error_message_i : in  string  := ""; -- string to be added in front of generated message
    message_prolog_i            : in  string  := ""; -- string to be added in front of generated message
    expected_data_mask_i       : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
    expected_data_mask_i       : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
    );
    );
 
 
  -- generate single read cycle and return read data via read_data_o
  -- generate single read cycle and return read data via read_data_o
  procedure wb_read(
  procedure wb_read(
    address_i                  : in  integer; -- address to read from
    address_i                  : in  integer; -- address to read from
    read_data_o                : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output
    read_data_o                : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t -- outgoing wb signals
    signal o                    : out wishbone_bfm_master_out_t;  -- outgoing wb signals
 
    verbose_mode_i              : in  integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output
 
    message_prolog_i            : in  string  := "" -- string to be added in front of generated message
    );
    );
  ---------------------------------------------------------------------- 
  ---------------------------------------------------------------------- 
end;
end;
 
 
-- package body ------------------------------------------------------
-- package body ------------------------------------------------------
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  procedure wb_write(
  procedure wb_write(
    address_i                  : in  integer; -- address to write to
    address_i                  : in  integer; -- address to write to
    data_i                     : in  integer; -- data value to be written
    data_i                     : in  integer; -- data value to be written
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    display_error_message_i    : in  integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
    verbose_mode_i              : in  integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
    additional_error_message_i : in  string  := "" -- string to be added in front of generated message
    message_prolog_i            : in  string  := "" -- string to be added in front of generated message
    ) is
    ) is
    ---------------------------------------------------------------------- 
    ---------------------------------------------------------------------- 
  begin
  begin
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
    o.dat       <= to_std_logic_vector(data_i, wishbone_data_width_c);
    o.dat       <= to_std_logic_vector(data_i, wishbone_data_width_c);
Line 164... Line 166...
    o.lock      <= '1';
    o.lock      <= '1';
    o.sel       <= (others => '1');
    o.sel       <= (others => '1');
    o.stb       <= '1';
    o.stb       <= '1';
    o.tga       <= (others => '0');
    o.tga       <= (others => '0');
    o.tgc       <= (others => '0');
    o.tgc       <= (others => '0');
    if (display_error_message_i = 2) then
    if (verbose_mode_i = 2) then
      report additional_error_message_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4);
      report message_prolog_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4);
    end if;
    end if;
 
 
    -- ack handling
    -- ack handling
    loop
    loop
      wait until rising_edge(i.clk);
      wait until rising_edge(i.clk);
Line 183... Line 185...
  ----------------------------------------------------------------------
  ----------------------------------------------------------------------
  procedure wb_read(
  procedure wb_read(
    address_i   : in  integer;   -- address to read from
    address_i   : in  integer;   -- address to read from
    read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output
    read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output
    signal i    : in  wishbone_bfm_master_in_t;  -- incoming wb signals
    signal i    : in  wishbone_bfm_master_in_t;  -- incoming wb signals
    signal o    : out wishbone_bfm_master_out_t  -- outgoing wb signals
    signal o                : out wishbone_bfm_master_out_t;  -- outgoing wb signals
 
    verbose_mode_i          : in  integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output
 
    message_prolog_i        : in  string  := "" -- string to be added in front of generated message
    ) is
    ) is
    ----------------------------------------------------------------------
    ----------------------------------------------------------------------
  begin
  begin
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
    o.dat       <= (others => 'U');
    o.dat       <= (others => 'U');
Line 207... Line 211...
      if (i.ack = '1') then
      if (i.ack = '1') then
        exit;
        exit;
      end if;
      end if;
    end loop;
    end loop;
    o           <= wb_bfm_master_out_idle_c; -- reset bus
    o           <= wb_bfm_master_out_idle_c; -- reset bus
 
 
 
    if (verbose_mode_i = 2) then  -- output all
 
      report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
 
        " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
 
        severity note;
  end wb_read;
  end wb_read;
  ------------------------------------------------------------------------
  ------------------------------------------------------------------------
  ------------------------------------------------------------------------
  ------------------------------------------------------------------------
  procedure wb_read(
  procedure wb_read(
    address_i                  : in  integer; -- address to read from
    address_i                  : in  integer; -- address to read from
    expected_data_i            : in  integer; -- data to be compared to read data; if different an error message is generated
    expected_data_i            : in  integer; -- data to be compared to read data; if different an error message is generated
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    signal o                   : out wishbone_bfm_master_out_t; -- outgoing wb signals
    display_error_message_i    : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
    verbose_mode_i              : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
    additional_error_message_i : in  string  := ""; -- string to be added in front of generated message
    message_prolog_i            : in  string  := ""; -- string to be added in front of generated message
    expected_data_mask_i       : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
    expected_data_mask_i       : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
    ) is
    ) is
    ----------------------------------------------------------------------
    ----------------------------------------------------------------------
    variable readdata_v : std_logic_vector (31 downto 0);
    variable readdata_v : std_logic_vector (31 downto 0);
    variable diff_v     : integer;
    variable diff_v     : integer;
Line 228... Line 237...
  begin
  begin
    wb_read(address_i,readdata_v,i,o); -- read from bus
    wb_read(address_i,readdata_v,i,o); -- read from bus
 
 
    diff_v     := to_integer(readdata_v) - expected_data_i;
    diff_v     := to_integer(readdata_v) - expected_data_i;
 
 
    if (display_error_message_i = 1) then -- output errors only
    if (verbose_mode_i = 1) then -- output errors only
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
        report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
        report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4)
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4)
          severity error;
          severity error;
      end if;
      end if;
    elsif (display_error_message_i = 2) then  -- output all
    elsif (verbose_mode_i = 2) then  -- output all
      report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
      report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
        " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
        " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
        severity note;
        severity note;
    elsif (display_error_message_i = 3) then  -- output filter
    elsif (verbose_mode_i = 3) then  -- output filter
      if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /=
      if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /=
          to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
          to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
        report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
        report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
          " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
          " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
          severity note;
          severity note;
      end if;
      end if;
    elsif display_error_message_i = 4 then
    elsif verbose_mode_i = 4 then
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
        report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
        report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
          severity error;
          severity error;
      end if;
      end if;
    end if;
    end if;
  end wb_read;
  end wb_read;

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