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[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [convert_pkg.vhd] - Diff between revs 2 and 4

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---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----                                                              ---- 
----  This is a universal type conversion library for VHDL. With  ----
 
----  the contained overloaded functions conversions from any to  ----
 
----  any of the following data types are possible:               ----
 
----                                                              ----
 
----    std_logic_vector                                          ----
 
----    std_ulogic_vector                                         ----
 
----    unsigned                                                  ----
 
----    signed                                                    ----
 
----    bit_vector                                                ----
 
----    integer                                                   ----
 
----    string                                                    ----
 
----                                                              ----
 
----  To use them just add the prefix "to_" to the desired result ----
 
----  type with the source type in braces.                        ----
 
----  E.g. conversion from integer to std_logic_vector:           ----
 
----    destination<=to_std_logic_vector(source);                 ----
 
----                                                              ---- 
 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----                                                              ---- 
----                                                              ---- 
 
----  This file contains some type conversion functions.          ----
 
----                                                              ---- 
----  To Do:                                                      ---- 
----  To Do:                                                      ---- 
----    -                                                         ---- 
----    -                                                         ---- 
----                                                              ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----  Author(s):                                                  ---- 
----      - First & Last Name, email@opencores.org                ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
--    SVN information
----    SVN information
--
----
--      $URL:  $
----      $URL:  $
-- $Revision:  $
---- $Revision:  $
--     $Date:  $
----     $Date:  $
--   $Author:  $
----   $Author:  $
--       $Id:  $
----       $Id:  $
--
 
---------------------------------------------------------------------- 
---------------------------------------------------------------------- 
----                                                              ---- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- This source file may be used and distributed without         ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----                                                              ---- 
----------------------------------------------------------------------
----------------------------------------------------------------------
--============================================================================
-- library -----------------------------------------------------------
--============================================================================
 
LIBRARY ieee;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_arith.ALL;
--============================================================================
 
 
 
 
 
--============================================================================
-- package -----------------------------------------------------------
PACKAGE convert_pkg IS
PACKAGE convert_pkg IS
 
 
  FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector;
  FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector;
 
 
  FUNCTION to_integer(input : std_logic_vector) RETURN integer;
  FUNCTION to_integer(input : std_logic_vector) RETURN integer;
  FUNCTION to_string(int             : integer; base : integer := 10; length : integer := 0) RETURN string;
  FUNCTION to_string(int             : integer; base : integer := 10; length : integer := 0) RETURN string;
  FUNCTION to_string(slv             : std_logic_vector; base : integer; length : integer) RETURN string;
  FUNCTION to_string(slv             : std_logic_vector; base : integer; length : integer) RETURN string;
 
 
END convert_pkg;
END convert_pkg;
--============================================================================
 
 
 
--============================================================================
-- package body ------------------------------------------------------
PACKAGE BODY convert_pkg IS
PACKAGE BODY convert_pkg IS
  --==========================================================================
  ----------------------------------------------------------------------
  FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS
  FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS
  BEGIN
  BEGIN
    RETURN std_logic_vector(conv_unsigned(input, length));
    RETURN std_logic_vector(conv_unsigned(input, length));
  END;
  END;
 
  ----------------------------------------------------------------------
  FUNCTION to_integer(input : std_logic_vector) RETURN integer IS
  FUNCTION to_integer(input : std_logic_vector) RETURN integer IS
  BEGIN
  BEGIN
    RETURN conv_integer(unsigned(input));
    RETURN conv_integer(unsigned(input));
  END;
  END;
 
  ----------------------------------------------------------------------
  --==========================================================================
 
  FUNCTION to_char(int : integer) RETURN character IS
  FUNCTION to_char(int : integer) RETURN character IS
    VARIABLE c : character;
    VARIABLE c : character;
  BEGIN
  BEGIN
    CASE int IS
    CASE int IS
      WHEN 0      => c := '0';
      WHEN 0      => c := '0';
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      WHEN 35     => c := 'Z';
      WHEN 35     => c := 'Z';
      WHEN OTHERS => c := '?';
      WHEN OTHERS => c := '?';
    END CASE;
    END CASE;
    RETURN c;
    RETURN c;
  END to_char;
  END to_char;
  --========================================================================
  ----------------------------------------------------------------------
  -- convert integer to string using specified base
 
  -- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
 
  -- if base=0 convert to 32 bit hex
 
  FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS
  FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS
 
 
    VARIABLE temp    : string(1 TO 1000);
    VARIABLE temp    : string(1 TO 1000);
    VARIABLE num     : integer;
    VARIABLE num     : integer;
    VARIABLE abs_int : integer;
    VARIABLE abs_int : integer;
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      ELSE
      ELSE
        RETURN temp(1 TO len);
        RETURN temp(1 TO len);
      END IF;
      END IF;
    END IF;
    END IF;
  END to_string;
  END to_string;
 
  ----------------------------------------------------------------------
  --========================================================================
 
  FUNCTION to_string(slv : std_logic_vector) RETURN string IS
  FUNCTION to_string(slv : std_logic_vector) RETURN string IS
 
 
    VARIABLE hexlen  : integer;
    VARIABLE hexlen  : integer;
    VARIABLE longslv : std_logic_vector(131 DOWNTO 0) := (OTHERS => '0');
    VARIABLE longslv : std_logic_vector(131 DOWNTO 0) := (OTHERS => '0');
    VARIABLE hex     : string(1 TO 32);
    VARIABLE hex     : string(1 TO 32);
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        WHEN OTHERS => hex(hexlen -I) := '?';
        WHEN OTHERS => hex(hexlen -I) := '?';
      END CASE;
      END CASE;
    END LOOP;
    END LOOP;
    RETURN hex(1 TO hexlen);
    RETURN hex(1 TO hexlen);
  END to_string;
  END to_string;
 
  ----------------------------------------------------------------------
  --========================================================================
 
  FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS
  FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS
 
 
  BEGIN
  BEGIN
    RETURN to_string(to_integer(slv), base, length);
    RETURN to_string(to_integer(slv), base, length);
  END to_string;
  END to_string;
 
  ----------------------------------------------------------------------
end package body;
end package body;
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---- end of file                                                  ---- 
---- end of file                                                  ---- 
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