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---- ----
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- ----
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---- This is a universal type conversion library for VHDL. With ----
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---- the contained overloaded functions conversions from any to ----
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---- any of the following data types are possible: ----
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---- ----
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---- std_logic_vector ----
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---- std_ulogic_vector ----
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---- unsigned ----
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---- signed ----
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---- bit_vector ----
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---- integer ----
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---- string ----
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---- ----
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---- To use them just add the prefix "to_" to the desired result ----
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---- type with the source type in braces. ----
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---- E.g. conversion from integer to std_logic_vector: ----
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---- destination<=to_std_logic_vector(source); ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- ----
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---- This file contains some type conversion functions. ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- - ----
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---- - ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- - First & Last Name, email@opencores.org ----
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---- - Sinx, sinx@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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-- SVN information
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---- SVN information
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--
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----
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-- $URL: $
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---- $URL: $
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-- $Revision: $
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---- $Revision: $
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-- $Date: $
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---- $Date: $
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-- $Author: $
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---- $Author: $
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-- $Id: $
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---- $Id: $
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--
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---- ----
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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--============================================================================
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-- library -----------------------------------------------------------
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--============================================================================
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_arith.ALL;
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USE ieee.std_logic_arith.ALL;
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--============================================================================
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--============================================================================
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-- package -----------------------------------------------------------
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PACKAGE convert_pkg IS
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PACKAGE convert_pkg IS
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FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector;
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FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector;
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FUNCTION to_integer(input : std_logic_vector) RETURN integer;
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FUNCTION to_integer(input : std_logic_vector) RETURN integer;
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FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string;
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FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string;
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FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string;
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FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string;
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END convert_pkg;
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END convert_pkg;
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--============================================================================
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--============================================================================
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-- package body ------------------------------------------------------
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PACKAGE BODY convert_pkg IS
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PACKAGE BODY convert_pkg IS
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--==========================================================================
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----------------------------------------------------------------------
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FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS
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FUNCTION to_std_logic_vector(input : integer; length : integer) RETURN std_logic_vector IS
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BEGIN
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BEGIN
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RETURN std_logic_vector(conv_unsigned(input, length));
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RETURN std_logic_vector(conv_unsigned(input, length));
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END;
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END;
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FUNCTION to_integer(input : std_logic_vector) RETURN integer IS
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FUNCTION to_integer(input : std_logic_vector) RETURN integer IS
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BEGIN
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BEGIN
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RETURN conv_integer(unsigned(input));
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RETURN conv_integer(unsigned(input));
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END;
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END;
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--==========================================================================
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FUNCTION to_char(int : integer) RETURN character IS
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FUNCTION to_char(int : integer) RETURN character IS
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VARIABLE c : character;
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VARIABLE c : character;
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BEGIN
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BEGIN
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CASE int IS
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CASE int IS
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WHEN 0 => c := '0';
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WHEN 0 => c := '0';
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WHEN 35 => c := 'Z';
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WHEN 35 => c := 'Z';
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WHEN OTHERS => c := '?';
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WHEN OTHERS => c := '?';
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END CASE;
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END CASE;
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RETURN c;
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RETURN c;
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END to_char;
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END to_char;
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--========================================================================
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-- convert integer to string using specified base
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-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
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-- if base=0 convert to 32 bit hex
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FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS
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FUNCTION to_string(int : integer; base : integer := 10; length : integer := 0) RETURN string IS
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VARIABLE temp : string(1 TO 1000);
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VARIABLE temp : string(1 TO 1000);
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VARIABLE num : integer;
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VARIABLE num : integer;
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VARIABLE abs_int : integer;
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VARIABLE abs_int : integer;
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ELSE
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ELSE
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RETURN temp(1 TO len);
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RETURN temp(1 TO len);
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END IF;
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END IF;
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END IF;
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END IF;
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END to_string;
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END to_string;
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--========================================================================
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FUNCTION to_string(slv : std_logic_vector) RETURN string IS
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FUNCTION to_string(slv : std_logic_vector) RETURN string IS
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VARIABLE hexlen : integer;
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VARIABLE hexlen : integer;
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VARIABLE longslv : std_logic_vector(131 DOWNTO 0) := (OTHERS => '0');
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VARIABLE longslv : std_logic_vector(131 DOWNTO 0) := (OTHERS => '0');
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VARIABLE hex : string(1 TO 32);
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VARIABLE hex : string(1 TO 32);
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WHEN OTHERS => hex(hexlen -I) := '?';
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WHEN OTHERS => hex(hexlen -I) := '?';
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END CASE;
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END CASE;
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END LOOP;
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END LOOP;
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RETURN hex(1 TO hexlen);
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RETURN hex(1 TO hexlen);
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END to_string;
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END to_string;
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--========================================================================
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FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS
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FUNCTION to_string(slv : std_logic_vector; base : integer; length : integer) RETURN string IS
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BEGIN
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BEGIN
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RETURN to_string(to_integer(slv), base, length);
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RETURN to_string(to_integer(slv), base, length);
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END to_string;
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END to_string;
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----------------------------------------------------------------------
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end package body;
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end package body;
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---- end of file ----
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---- end of file ----
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