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---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- SVN information
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---- SVN information
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----
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----
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---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/wishbone_pkg.vhd $
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---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/wishbone_pkg.vhd $
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---- $Revision: 14 $
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---- $Revision: 22 $
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---- $Date: 2018-07-22 16:27:41 +0200 (Sun, 22 Jul 2018) $
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---- $Date: 2018-08-01 12:06:31 +0200 (Wed, 01 Aug 2018) $
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---- $Author: sinx $
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---- $Author: sinx $
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---- $Id: wishbone_pkg.vhd 14 2018-07-22 14:27:41Z sinx $
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---- $Id: wishbone_pkg.vhd 22 2018-08-01 10:06:31Z sinx $
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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-- package -----------------------------------------------------------
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-- package -----------------------------------------------------------
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package wishbone_pkg is
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package wishbone_pkg is
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subtype wishbone_address_t is std_logic_vector(wishbone_address_width_c-1 downto 0);
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subtype wishbone_address_t is std_logic_vector(wishbone_address_width_c-1 downto 0);
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subtype wishbone_data_t is std_logic_vector(wishbone_data_width_c-1 downto 0);
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subtype wishbone_data_t is std_logic_vector(wishbone_data_width_c-1 downto 0);
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subtype wishbone_byte_select_t is std_logic_vector((wishbone_address_width_c/8)-1 downto 0);
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subtype wishbone_byte_select_t is std_logic_vector((wishbone_data_width_c/8)-1 downto 0);
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--subtype wishbone_cycle_type_t is std_logic_vector(2 downto 0);
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--subtype wishbone_cycle_type_t is std_logic_vector(2 downto 0);
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--subtype wishbone_burst_type_t is std_logic_vector(1 downto 0);
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--subtype wishbone_burst_type_t is std_logic_vector(1 downto 0);
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type wishbone_master_out_t is record
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type wishbone_master_out_t is record
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
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stb => '0',
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stb => '0',
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tga => (others=>'0'),
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tga => (others=>'0'),
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tgc => (others=>'0'),
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tgc => (others=>'0'),
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we => '0'
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we => '0'
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);
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);
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constant wb_slave_in_idle_c : wishbone_slave_in_t := wb_master_out_idle_c;
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constant wb_master_in_idle_c : wishbone_master_in_t := (
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dat => wishbone_data_of_unused_address_c,
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tgd => (others=>'0'),
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ack => '0',
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err => '0',
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rty => '0',
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int => '0'
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);
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constant wb_slave_out_idle_c : wishbone_slave_out_t := wb_master_in_idle_c;
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-- constant cc_dummy_address : std_logic_vector(wishbone_address_width_c-1 downto 0) :=(others => 'X');
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-- constant cc_dummy_address : std_logic_vector(wishbone_address_width_c-1 downto 0) :=(others => 'X');
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-- constant cc_dummy_data : std_logic_vector(wishbone_address_width_c-1 downto 0) := (others => 'X');
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-- constant cc_dummy_data : std_logic_vector(wishbone_address_width_c-1 downto 0) := (others => 'X');
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-- constant cc_dummy_sel : std_logic_vector(wishbone_data_width_c/8-1 downto 0) := (others => 'X');
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-- constant cc_dummy_sel : std_logic_vector(wishbone_data_width_c/8-1 downto 0) := (others => 'X');
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-- constant cc_dummy_slave_in : wishbone_slave_in_t :=('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
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-- constant cc_dummy_slave_in : wishbone_slave_in_t :=('0', '0', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
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