URL https://opencores.org/ocsvn/viterbi_decoder_axi4s/viterbi_decoder_axi4s/trunk

Subversion Repositories viterbi_decoder_axi4s

[/] [viterbi_decoder_axi4s/] [trunk/] [packages/] [pkg_components.vhd] - Diff between revs 2 and 6

Rev 2	Rev 6
Line 1...	Line 1...
`--!`	`--!`
`--! Copyright (C) 2011 - 2012 Creonic GmbH`	`--! Copyright (C) 2011 - 2014 Creonic GmbH`
`--!`	`--!`
`--! This file is part of the Creonic Viterbi Decoder, which is distributed`	`--! This file is part of the Creonic Viterbi Decoder, which is distributed`
`--! under the terms of the GNU General Public License version 2.`	`--! under the terms of the GNU General Public License version 2.`
`--!`	`--!`
`--! @file`	`--! @file`
Line 20...	Line 20...
`use dec_viterbi.pkg_param_derived.all;`	`use dec_viterbi.pkg_param_derived.all;`
`use dec_viterbi.pkg_types.all;`	`use dec_viterbi.pkg_types.all;`

`package pkg_components is`	`package pkg_components is`

	`component axi4s_buffer is`
	`generic (`
	`DATA_WIDTH : natural := 1`
	`);`
	`port (`
	`clk : in std_logic;`
	`rst : in std_logic;`

	`input : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
	`input_valid : in std_logic;`
	`input_last : in std_logic;`
	`input_accept : out std_logic;`

	`output : out std_logic_vector(DATA_WIDTH - 1 downto 0);`
	`output_valid : out std_logic;`
	`output_last : out std_logic;`
	`output_accept : in std_logic`
	`);`
	`end component axi4s_buffer;`

`component branch_distance is`	`component branch_distance is`
`generic(`	`generic(`
`EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0)`	`EDGE_WEIGHT : in std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0)`
`);`	`);`
`port(`	`port(`