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//Author : Alex Zhang (cgzhangwei@gmail.com)
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//Author : Alex Zhang (cgzhangwei@gmail.com)
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//Date : 03-11-2015
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//Date : 03-11-2015
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//Basic : How to storage the AXI info and data into sram or fifo.
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//Basic : How to storage the AXI info and data into sram or fifo.
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`include "wb2axi_parameters.vh"
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`include "wb2axi_parameters.vh"
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module axi_ingress (
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module axi_ingress (
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axi_clk,
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axi_clk,
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reset_n,
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reset_n,
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AXI_IF,
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AXI_IF,
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fifo_full,
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fifo_full,
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fifo_addr_info,
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fifo_addr_info,
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fifo_data_info,
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fifo_data_info,
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fifo_addr_wr,
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fifo_addr_wr,
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fifo_data_wr
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fifo_data_wr
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);
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);
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parameter AXI_WID_W = 5;
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parameter AXI_ID_W = `WB2AXI_AXI_ID_W ;
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parameter AXI_ADDR_W = `WB2AXI_AXI_ADDR_W ;
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parameter AXI_DATA_W = `WB2AXI_AXI_DATA_W ;
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parameter AXI_PROT_W = `WB2AXI_AXI_PROT_W ;
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parameter AXI_STB_W = `WB2AXI_AXI_STB_W ;
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parameter AXI_LEN_W = `WB2AXI_AXI_LEN_W ;
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parameter AXI_SIZE_W = `WB2AXI_AXI_SIZE_W ;
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parameter AXI_BURST_W = `WB2AXI_AXI_BURST_W;
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parameter AXI_LOCK_W = `WB2AXI_AXI_LOCK_W ;
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parameter AXI_CACHE_W = `WB2AXI_AXI_CACHE_W;
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parameter AXI_RESP_W = `WB2AXI_AXI_RESP_W ;
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parameter AXI_MAX_RESP_W = 3;
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parameter AXI_MAX_RESP_W = 3;
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parameter FIFO_ADR_W = 10;
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parameter FIFO_DAT_W = 10;
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input axi_clk;
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input axi_clk;
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input reset_n;
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input reset_n;
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axi_if.target AXI_IF;
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axi_if.target AXI_IF;
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output fifo_full;
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output fifo_full;
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output [FIFO_AW-1:0] fifo_addr_info;
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output [FIFO_ADR_W-1:0] fifo_addr_info;
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output [FIFO_DW-1:0] fifo_data_info;
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output [FIFO_DAT_W-1:0] fifo_data_info;
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output reg fifo_addr_wr;
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output reg fifo_addr_wr;
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output reg fifo_data_wr;
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output reg fifo_data_wr;
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localparam ST_W = 2;
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localparam ST_W = 2;
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localparam ST_IDLE = 2'b00;
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localparam ST_IDLE = 2'b00;
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localparam ST_WDATA = 2'b01;
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localparam ST_WDATA = 2'b01;
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reg [ST_W-1:0] state;
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reg [ST_W-1:0] state;
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reg [ST_W-1:0] next_state;
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reg [ST_W-1:0] next_state;
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reg [AXI_MAX_RESP_W-1:0] bresp_pending_cnt; //responses pending to generate
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reg [AXI_MAX_RESP_W-1:0] bresp_pending_cnt; //responses pending to generate
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reg [AXI_WID_W-1:0] last_wid;
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reg [AXI_ID_W-1:0] last_wid;
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reg [FIFO_AW-1:0] fifo_addr_in;
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reg [FIFO_ADR_W-1:0] fifo_addr_in;
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reg [FIFO_DW-1:0] fifo_data_in;
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reg [FIFO_DAT_W-1:0] fifo_data_in;
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assign input_addr_event = AXI_IF.AWVALID & AXI_IF.AWREADY;
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assign input_addr_event = AXI_IF.AWVALID & AXI_IF.AWREADY;
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assign input_data_event = AXI_FI.WVALID & AXI_IF.WREADY;
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assign input_data_event = AXI_IF.WVALID & AXI_IF.WREADY;
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assign inc_bresp = AXI_IF.WLAST & input_data_event;
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assign inc_bresp = AXI_IF.WLAST & input_data_event;
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assign dec_bresp = AXI_IF.BREADY & AXI_IF.BVALID;
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assign dec_bresp = AXI_IF.BREADY & AXI_IF.BVALID;
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assign bresp_cnt_max = (bresp_pending_cnt == AXI_MAX_RESP_VAL);
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assign bresp_cnt_max = (bresp_pending_cnt == AXI_MAX_RESP_VAL);
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always_comb begin
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always_comb begin
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assign AXI_IF.ARREADY = 0;
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assign AXI_IF.ARREADY = 0;
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assign AXI_IF.RDATA = 0;
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assign AXI_IF.RDATA = 0;
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assign AXI_IF.RRESP = 0;
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assign AXI_IF.RRESP = 0;
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assign AXI_IF.RLAST = 0;
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assign AXI_IF.RLAST = 0;
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assign AXI_IF.RVALID = 0;
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assign AXI_IF.RVALID = 0;
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assign AIX_IF.AWREADY = (state ==ST_IDLE || state==ST_WDATA) & ~fifo_full & ~bresp_cnt_max;
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assign AXI_IF.AWREADY = (state ==ST_IDLE || state==ST_WDATA) & ~fifo_full & ~bresp_cnt_max;
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assign AXI_IF.WREADY = ~fifo_full & ~bresp_cnt_max;
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assign AXI_IF.WREADY = ~fifo_full & ~bresp_cnt_max;
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assign fifo_addr_info = fifo_addr_in;
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assign fifo_addr_info = fifo_addr_in;
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assign fifo_data_info = fifo_data_in;
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assign fifo_data_info = fifo_data_in;
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