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https://opencores.org/ocsvn/wb2axi4/wb2axi4/trunk
[/] [wb2axi4/] [trunk/] [rtl/] [ifaces/] [wishbone_if.sv] - Diff between revs 2 and 3
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Rev 3 |
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// TGD : WID,
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// TGD : WID,
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// TGA : AWID| ARID,
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// TGA : AWID| ARID,
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interface wishbone_if #(
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interface wishbone_if #(
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WB_ADR_WIDTH = 32,
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WB_ADR_WIDTH = 32,
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WB_BTE_WIDTH = 2 ,
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WB_BTE_WIDTH = 2 ,
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WB_CIT_WIDTH = 3 ,
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WB_CTI_WIDTH = 3 ,
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WB_DAT_WIDTH = 32,
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WB_DAT_WIDTH = 32,
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WB_TGA_WIDTH = 8,
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WB_TGA_WIDTH = 8,
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WB_TGD_WIDTH = 8,
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WB_TGD_WIDTH = 8,
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WB_TGC_WIDTH = 4,
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WB_TGC_WIDTH = 4,
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WB_SEL_WIDTH = 4
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WB_SEL_WIDTH = 4
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);
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);
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logic [WB_ADR_WIDTH -1 : 0] ADR;
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logic [WB_TGA_WIDTH -1 :0 ] TGA;
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logic [WB_DAT_WIDTH -1 : 0] DAT_I;
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logic [WB_DAT_WIDTH -1 : 0] DAT_I;
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logic [WB_DAT_WIDTH -1 : 0] DAT_O;
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logic [WB_TGD_WIDTH -1 : 0] TGD_I;
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logic [WB_TGD_WIDTH -1 : 0] TGD_I;
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logic [WB_DAT_WIDTH -1 : 0] DAT_O;
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logic [WB_TGD_WIDTH -1 : 0] TGD_O;
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logic [WB_TGD_WIDTH -1 : 0] TGD_O;
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logic ACK_I;
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logic WE;
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logic [WB_ADR_WIDTH -1 : 0] ADR_O;
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logic [WB_SEL_WIDTH -1 : 0] SEL;
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logic CYC_O;
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logic STB;
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logic ERR_I;
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logic ACK;
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logic LOCK_O;
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logic CYC;
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logic RTY_I;
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logic ERR;
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logic [WB_SEL_WIDTH -1 : 0] SEL_O;
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logic LOCK;
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logic STB_O;
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logic [WB_BTE_WIDTH -1 :0 ] BTE;
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logic [WB_TGA_WIDTH -1 :0 ] TGA_O;
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logic RTY;
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logic [WB_TGA_WIDTH -1 :0 ] TGC_O;
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logic [WB_CTI_WIDTH -1 :0 ] CTI;
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logic WE_O;
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logic [WB_TGA_WIDTH -1 :0 ] TGC;
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logic [WB_BTE_WIDTH -1 :0 ] BTE_O;
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logic [WB_BTE_WIDTH -1 :0 ] BTE_I;
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logic [WB_CTI_WIDTH -1 :0 ] CTI_O;
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logic [WB_CTI_WIDTH -1 :0 ] CTI_I;
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logic ACK_O;
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logic [WB_ADR_WIDTH -1 : 0] ADR_I;
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logic CYC_I;
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logic ERR_O;
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logic LOCK_I;
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logic RTY_O;
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logic [WB_SEL_WIDTH -1 : 0] SEL_I;
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logic [WB_TGA_WIDTH -1 :0 ] TGA_I;
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logic [WB_TGA_WIDTH -1 :0 ] TGC_I;
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logic WE_I;
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modport master(
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modport master(
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output ADR_O,
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output ADR ,
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output TGA_O,
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output TGA ,
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input DAT_I,
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input DAT_I,
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input TGD_I,
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input TGD_I,
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output DAT_O,
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output DAT_O,
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output TGD_O,
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output TGD_O,
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output WE_O,
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output WE ,
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output SEL_O,
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output SEL ,
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output STB_O,
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output STB ,
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input ACK_I,
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input ACK ,
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output CYC_O,
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output CYC ,
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input ERR_I,
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input ERR ,
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output LOCK_O,
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output LOCK ,
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output BTE_O,
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output BTE ,
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input RTY_I,
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input RTY ,
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output TGC_O
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output CTI ,
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output TGC
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);
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);
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modport slave(
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modport slave(
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output ADR_I,
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input ADR ,
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output TGA_I,
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input TGA ,
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input DAT_I,
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input TGD_I,
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output DAT_O,
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output DAT_O,
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output TGD_O,
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output TGD_O,
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output WE_I,
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input DAT_I,
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output SEL_I,
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input TGD_I,
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output STB_I,
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input WE ,
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input ACK_O,
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input SEL ,
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output CYC_I,
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input STB ,
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input ERR_O,
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output ACK ,
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output LOCK_I,
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input CYC ,
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input BTE_I,
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output ERR ,
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input RTY_O,
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input LOCK ,
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output TGC_I
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input BTE ,
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output RTY ,
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input CTI ,
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input TGC
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);
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);
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endinterface
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endinterface
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