//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: serirq_host.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
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//// $Id: serirq_host.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
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//// serirq_host.v - SERIRQ Host Controller ////
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//// serirq_host.v - SERIRQ Host Controller ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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//// Author: ////
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//// Author: ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// - Howard M. Harte (hharte@opencores.org) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// Copyright (C) 2008 Howard M. Harte ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 1 ns
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`timescale 1 ns / 1 ns
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`include "../../rtl/verilog/serirq_defines.v"
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`include "../../rtl/verilog/serirq_defines.v"
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module serirq_host(clk_i, nrst_i,
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module serirq_host(clk_i, nrst_i,
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serirq_mode_i, irq_o,
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serirq_mode_i, irq_o,
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serirq_o, serirq_i, serirq_oe
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serirq_o, serirq_i, serirq_oe
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);
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);
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// Wishbone Slave Interface
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// Wishbone Slave Interface
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input clk_i;
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input clk_i;
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input nrst_i; // Active low reset.
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input nrst_i; // Active low reset.
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input serirq_mode_i; // Mode selection, 0=Continuous, 1=Quiet
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input serirq_mode_i; // Mode selection, 0=Continuous, 1=Quiet
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// SERIRQ Master Interface
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// SERIRQ Master Interface
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output reg serirq_o; // SERIRQ output
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output reg serirq_o; // SERIRQ output
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input serirq_i; // SERIRQ Input
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input serirq_i; // SERIRQ Input
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output reg serirq_oe; // SERIRQ Output Enable
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output reg serirq_oe; // SERIRQ Output Enable
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output reg [31:0] irq_o; // IRQ Output Bus
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output reg [31:0] irq_o; // IRQ Output Bus
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reg [12:0] state; // Current state
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reg [12:0] state; // Current state
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reg [4:0] irq_cnt; // IRQ Frame counter
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reg [4:0] irq_cnt; // IRQ Frame counter
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reg [2:0] start_cnt; // START counter
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reg [2:0] start_cnt; // START counter
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reg [2:0] stop_cnt; // STOP counter
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reg [2:0] stop_cnt; // STOP counter
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reg current_mode;
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reg current_mode;
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always @(posedge clk_i or negedge nrst_i)
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always @(posedge clk_i or negedge nrst_i)
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if(~nrst_i)
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if(~nrst_i)
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begin
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begin
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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serirq_oe <= 1'b0;
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serirq_oe <= 1'b0;
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serirq_o <= 4'b1;
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serirq_o <= 4'b1;
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irq_cnt <= 5'h00;
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irq_cnt <= 5'h00;
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start_cnt <= 3'b000;
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start_cnt <= 3'b000;
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stop_cnt <= 2'b00;
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stop_cnt <= 2'b00;
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irq_o <= 32'hFFFFFFFF;
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irq_o <= 32'hFFFFFFFF;
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current_mode <= `SERIRQ_MODE_CONTINUOUS;
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current_mode <= `SERIRQ_MODE_CONTINUOUS;
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end
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end
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else begin
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else begin
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case(state)
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case(state)
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`SERIRQ_ST_IDLE:
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`SERIRQ_ST_IDLE:
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begin
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begin
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serirq_oe <= 1'b0;
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serirq_oe <= 1'b0;
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start_cnt <= 3'b000;
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start_cnt <= 3'b000;
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stop_cnt <= 2'b00;
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stop_cnt <= 2'b00;
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serirq_o <= 1'b1;
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serirq_o <= 1'b1;
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if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_i == 1'b0)) begin
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if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_i == 1'b0)) begin
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start_cnt <= 3'b010;
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start_cnt <= 3'b010;
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serirq_o <= 1'b0;
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serirq_o <= 1'b0;
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serirq_oe <= 1'b1;
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serirq_oe <= 1'b1;
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state <= `SERIRQ_ST_START;
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state <= `SERIRQ_ST_START;
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end
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end
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else if(current_mode == `SERIRQ_MODE_CONTINUOUS)
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else if(current_mode == `SERIRQ_MODE_CONTINUOUS)
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begin
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begin
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start_cnt <= 3'b000;
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start_cnt <= 3'b000;
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state <= `SERIRQ_ST_START;
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state <= `SERIRQ_ST_START;
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end
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end
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else if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_mode_i == `SERIRQ_MODE_CONTINUOUS))
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else if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_mode_i == `SERIRQ_MODE_CONTINUOUS))
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begin // Switch to Continuous mode by starting a new cycle to inform the slaves.
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begin // Switch to Continuous mode by starting a new cycle to inform the slaves.
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start_cnt <= 3'b000;
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start_cnt <= 3'b000;
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state <= `SERIRQ_ST_START;
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state <= `SERIRQ_ST_START;
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end
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end
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else
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else
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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end
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end
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`SERIRQ_ST_START:
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`SERIRQ_ST_START:
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begin
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begin
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serirq_o <= 1'b0;
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serirq_o <= 1'b0;
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serirq_oe <= 1'b1;
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serirq_oe <= 1'b1;
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irq_cnt <= 5'h00;
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irq_cnt <= 5'h00;
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start_cnt <= start_cnt + 1;
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start_cnt <= start_cnt + 1;
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if(start_cnt == 3'b111) begin
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if(start_cnt == 3'b111) begin
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state <= `SERIRQ_ST_START_R;
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state <= `SERIRQ_ST_START_R;
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end
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end
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else begin
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else begin
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state <= `SERIRQ_ST_START;
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state <= `SERIRQ_ST_START;
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end
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end
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end
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end
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`SERIRQ_ST_START_R:
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`SERIRQ_ST_START_R:
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begin
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begin
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serirq_o <= 1'b1;
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serirq_o <= 1'b1;
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state <= `SERIRQ_ST_START_T;
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state <= `SERIRQ_ST_START_T;
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end
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end
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`SERIRQ_ST_START_T:
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`SERIRQ_ST_START_T:
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begin
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begin
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serirq_oe <= 1'b0;
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serirq_oe <= 1'b0;
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state <= `SERIRQ_ST_IRQ;
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state <= `SERIRQ_ST_IRQ;
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end
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end
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`SERIRQ_ST_IRQ:
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`SERIRQ_ST_IRQ:
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begin
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begin
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state <= `SERIRQ_ST_IRQ_R;
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state <= `SERIRQ_ST_IRQ_R;
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end
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end
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`SERIRQ_ST_IRQ_R:
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`SERIRQ_ST_IRQ_R:
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begin
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begin
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irq_o[irq_cnt] <= (serirq_i == 1'b0 ? 1'b0 : 1'b1);
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irq_o[irq_cnt] <= (serirq_i == 1'b0 ? 1'b0 : 1'b1);
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state <= `SERIRQ_ST_IRQ_T;
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state <= `SERIRQ_ST_IRQ_T;
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end
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end
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`SERIRQ_ST_IRQ_T:
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`SERIRQ_ST_IRQ_T:
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begin
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begin
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if(irq_cnt == 5'h1f) begin
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if(irq_cnt == 5'h1f) begin
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state <= `SERIRQ_ST_STOP;
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state <= `SERIRQ_ST_STOP;
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end else begin
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end else begin
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state <= `SERIRQ_ST_IRQ;
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state <= `SERIRQ_ST_IRQ;
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irq_cnt <= irq_cnt + 1;
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irq_cnt <= irq_cnt + 1;
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end
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end
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end
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end
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`SERIRQ_ST_STOP:
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`SERIRQ_ST_STOP:
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begin
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begin
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serirq_o <= 1'b0;
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serirq_o <= 1'b0;
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serirq_oe <= 1'b1;
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serirq_oe <= 1'b1;
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stop_cnt <= stop_cnt + 1;
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stop_cnt <= stop_cnt + 1;
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if(stop_cnt == (serirq_mode_i ? 2'b01 : 2'b10)) begin
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if(stop_cnt == (serirq_mode_i ? 2'b01 : 2'b10)) begin
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state <= `SERIRQ_ST_STOP_R;
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state <= `SERIRQ_ST_STOP_R;
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end
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end
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else begin
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else begin
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state <= `SERIRQ_ST_STOP;
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state <= `SERIRQ_ST_STOP;
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end
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end
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end
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end
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`SERIRQ_ST_STOP_R:
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`SERIRQ_ST_STOP_R:
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begin
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begin
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serirq_o <= 1'b1;
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serirq_o <= 1'b1;
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state <= `SERIRQ_ST_STOP_T;
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state <= `SERIRQ_ST_STOP_T;
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end
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end
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`SERIRQ_ST_STOP_T:
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`SERIRQ_ST_STOP_T:
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begin
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begin
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serirq_oe <= 1'b0;
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serirq_oe <= 1'b0;
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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current_mode <= serirq_mode_i;
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current_mode <= serirq_mode_i;
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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