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//
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//////////////////////////////////////////////////////////////////////
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//
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//// ////
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//
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module asram_if(
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module asram_if(
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inout [15:0] sram_dq, // SRAM Data bus 16 Bits
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inout [15:0] sram_dq, // SRAM Data bus 16 Bits
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output [17:0] sram_addr, // SRAM Address bus 18 Bits
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output [17:0] sram_addr, // SRAM Address bus 18 Bits
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output sram_ub_n, // SRAM High-byte Data Mask
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output sram_ub_n, // SRAM High-byte Data Mask
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assign sram_dq = wb_lo_we_o ? wb_lo_dat_o : 16'hzz;
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assign sram_dq = wb_lo_we_o ? wb_lo_dat_o : 16'hzz;
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assign sram_addr = wb_lo_adr_o[18:1];
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assign sram_addr = wb_lo_adr_o[18:1];
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assign sram_ub_n = ~wb_lo_sel_o[1];
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assign sram_ub_n = ~wb_lo_sel_o[1];
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assign sram_lb_n = ~wb_lo_sel_o[0];
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assign sram_lb_n = ~wb_lo_sel_o[0];
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assign sram_we_n = ~wb_lo_we_o;
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assign sram_we_n = ~wb_lo_we_o;
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// assign sram_ce_n = ~(wb_lo_stb_o & wb_lo_cyc_o);
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assign sram_ce_n = 1'b0;
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assign sram_ce_n = 1'b0;
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assign sram_oe_n = wb_lo_we_o;
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assign sram_oe_n = wb_lo_we_o;
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endmodule
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endmodule
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