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//
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//////////////////////////////////////////////////////////////////////
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//
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//// ////
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//
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module async_mem_if( async_dq, async_addr, async_ub_n, async_lb_n,
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module async_mem_if( async_dq, async_addr, async_ub_n, async_lb_n,
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async_we_n, async_ce_n, async_oe_n,
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async_we_n, async_ce_n, async_oe_n,
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i,
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i,
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// --------------------------------------------------------------------
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// --------------------------------------------------------------------
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// state machine outputs
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// state machine outputs
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wire assert_ce = (state != STATE_IDLE);
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wire assert_ce = (state != STATE_IDLE);
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// wire assert_op = (state == STATE_OP_HOLD) | (state == STATE_CE_HOLD);
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wire assert_op = (state == STATE_OP_HOLD);
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wire assert_op = (state == STATE_OP_HOLD);
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assign wb_lo_ack_i = ( (state == STATE_OP_HOLD) & ~wait_for_counter & zero_ce_hold) |
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assign wb_lo_ack_i = ( (state == STATE_OP_HOLD) & ~wait_for_counter & zero_ce_hold) |
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( (state == STATE_CE_HOLD) & ~wait_for_counter );
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( (state == STATE_CE_HOLD) & ~wait_for_counter );
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