URL
https://opencores.org/ocsvn/wb_size_bridge/wb_size_bridge/trunk
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Rev 7 |
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Line 93... |
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end
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end
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32: begin
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32: begin
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initial
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initial
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begin
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$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
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$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
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$display( "###- wb_slave_model(): Not yet supported " );
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$stop();
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always @ (posedge clk_i)
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end
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if (we_i & cyc_i & stb_i & sel_i[0])
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ram[{adr_i[AWIDTH-1:2], 2'b00}] <= dat_i[7:0];
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always @ (posedge clk_i)
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if (we_i & cyc_i & stb_i & sel_i[1])
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ram[{adr_i[AWIDTH-1:2], 2'b01}] <= dat_i[15:8];
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always @ (posedge clk_i)
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if (we_i & cyc_i & stb_i & sel_i[2])
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ram[{adr_i[AWIDTH-1:2], 2'b10}] <= dat_i[23:16];
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always @ (posedge clk_i)
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if (we_i & cyc_i & stb_i & sel_i[3])
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ram[{adr_i[AWIDTH-1:2], 2'b11}] <= dat_i[31:24];
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assign dat_o = { ram[{adr_i[AWIDTH-1:2], 2'b11}], ram[{adr_i[AWIDTH-1:2], 2'b10}], ram[{adr_i[AWIDTH-1:2], 2'b01}], ram[{adr_i[AWIDTH-1:2], 2'b00}] };
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end
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end
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default: begin
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default: begin
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localparam SLAVE_SIZE = -1;
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localparam SLAVE_SIZE = -1;
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initial
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initial
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