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--
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-- Wishbone bus toolkit.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- wb_bus_upsize: bus upsizer. Currently only 8->16 bit bus resize is supported
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-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.
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-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus
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-- wb_out_reg: Wishbone bus compatible output register.
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-- wb_bus_resize: Wishbone bus resizer.
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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package components is
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component wb_bus_upsize
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generic (
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m_dat_width: positive := 8; -- master bus width
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m_adr_width: positive := 21; -- master bus width
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s_dat_width: positive := 16; -- slave bus width
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s_adr_width: positive := 20; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end component;
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component wb_bus_dnsize
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generic (
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m_dat_width: positive := 32; -- master bus width
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m_adr_width: positive := 20; -- master bus width
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s_dat_width: positive := 16; -- slave bus width
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s_adr_width: positive := 21; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end component;
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component wb_bus_resize
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generic (
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m_dat_width: positive := 32; -- master bus width
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m_adr_width: positive := 20; -- master bus width
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s_dat_width: positive := 16; -- slave bus width
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s_adr_width: positive := 21; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end component;
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component wb_ro_async_master
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generic (
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dat_width: positive;
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adr_width: positive;
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ab_rd_delay: positive
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);
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port (
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wb_clk_i: in std_logic;
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wb_rst_i: in std_logic := '0';
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-- interface to wb slave devices
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wb_adr_o: out std_logic_vector (adr_width-1 downto 0);
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wb_sel_o: out std_logic_vector ((dat_width/8)-1 downto 0);
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wb_dat_i: in std_logic_vector (dat_width-1 downto 0);
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wb_dat_o: out std_logic_vector (dat_width-1 downto 0);
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wb_cyc_o: out std_logic;
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wb_ack_i: in std_logic;
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wb_err_i: in std_logic := '-';
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wb_rty_i: in std_logic := '-';
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wb_we_o: out std_logic;
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wb_stb_o: out std_logic;
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-- interface to the asyncronous master device
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ab_dat: inout std_logic_vector (dat_width-1 downto 0) := (others => 'Z');
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ab_adr: in std_logic_vector (adr_width-1 downto 0) := (others => 'U');
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ab_rd_n: in std_logic := '1';
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ab_wr_n: in std_logic := '1';
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ab_ce_n: in std_logic := '1';
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ab_byteen_n: in std_logic_vector ((dat_width/8)-1 downto 0);
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ab_wait_n: out std_logic; -- wait-state request 'open-drain' output
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ab_waiths: out std_logic -- handshake-type totem-pole output
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);
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end component;
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component wb_async_master
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generic (
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dat_width: positive;
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adr_width: positive;
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ab_rd_delay: positive
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);
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port (
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wb_clk_i: in std_logic;
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wb_rst_i: in std_logic := '0';
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-- interface to wb slave devices
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wb_adr_o: out std_logic_vector (adr_width-1 downto 0);
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wb_sel_o: out std_logic_vector ((dat_width/8)-1 downto 0);
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wb_dat_i: in std_logic_vector (dat_width-1 downto 0);
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wb_dat_o: out std_logic_vector (dat_width-1 downto 0);
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wb_cyc_o: out std_logic;
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wb_ack_i: in std_logic;
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wb_err_i: in std_logic := '-';
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wb_rty_i: in std_logic := '-';
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wb_we_o: out std_logic;
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wb_stb_o: out std_logic;
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-- interface to the asyncronous master device
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ab_dat: inout std_logic_vector (dat_width-1 downto 0) := (others => 'Z');
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ab_adr: in std_logic_vector (adr_width-1 downto 0) := (others => 'U');
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ab_rd_n: in std_logic := '1';
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ab_wr_n: in std_logic := '1';
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ab_ce_n: in std_logic := '1';
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ab_byteen_n: in std_logic_vector ((dat_width/8)-1 downto 0);
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ab_wait_n: out std_logic; -- wait-state request 'open-drain' output
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ab_waiths: out std_logic -- handshake-type totem-pole output
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);
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end component;
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component wb_async_master_2
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generic (
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dat_width: positive;
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adr_width: positive;
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ab_rd_delay: positive
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);
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port (
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wb_clk_i: in std_logic;
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wb_rst_i: in std_logic := '0';
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-- interface to wb slave devices
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wb_adr_o: out std_logic_vector (adr_width-1 downto 0);
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wb_sel_o: out std_logic_vector ((dat_width/8)-1 downto 0);
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wb_dat_i: in std_logic_vector (dat_width-1 downto 0);
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wb_dat_o: out std_logic_vector (dat_width-1 downto 0);
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wb_cyc_o: out std_logic;
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wb_ack_i: in std_logic;
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wb_err_i: in std_logic := '-';
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wb_rty_i: in std_logic := '-';
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wb_we_o: out std_logic;
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wb_stb_o: out std_logic;
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-- interface to the asyncronous master device
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ab_dat: inout std_logic_vector (dat_width-1 downto 0) := (others => 'Z');
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ab_adr: in std_logic_vector (adr_width-1 downto 0) := (others => 'U');
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ab_rd_n: in std_logic := '1';
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ab_wr_n: in std_logic := '1';
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ab_ce_n: in std_logic := '1';
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ab_byteen_n: in std_logic_vector ((dat_width/8)-1 downto 0);
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ab_wait_n: out std_logic; -- wait-state request 'open-drain' output
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ab_waiths: out std_logic; -- handshake-type totem-pole output
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-- debug signals
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db_rd_pulse: out std_logic
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);
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end component;
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component wb_async_slave
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generic (
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dat_width: positive := 16;
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adr_width: positive := 20
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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-- interface for wait-state generator state-machine
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wait_state: in std_logic_vector (3 downto 0);
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-- interface to wishbone master device
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adr_i: in std_logic_vector (adr_width-1 downto 0);
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sel_i: in std_logic_vector ((adr_width/8)-1 downto 0);
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dat_i: in std_logic_vector (dat_width-1 downto 0);
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dat_o: out std_logic_vector (dat_width-1 downto 0);
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dat_oi: in std_logic_vector (dat_width-1 downto 0) := (others => '-');
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we_i: in std_logic;
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stb_i: in std_logic;
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ack_o: out std_logic := '0';
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ack_oi: in std_logic := '-';
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-- interface to async slave
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a_data: inout std_logic_vector (dat_width-1 downto 0) := (others => 'Z');
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a_addr: out std_logic_vector (adr_width-1 downto 0) := (others => 'U');
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a_rdn: out std_logic := '1';
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a_wrn: out std_logic := '1';
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a_cen: out std_logic := '1';
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-- byte-enable signals
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a_byen: out std_logic_vector ((dat_width/8)-1 downto 0)
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);
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end component;
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component wb_arbiter
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port (
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-- clk_i: in std_logic;
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rst_i: in std_logic := '0';
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-- interface to master device a
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a_we_i: in std_logic;
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a_stb_i: in std_logic;
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a_cyc_i: in std_logic;
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a_ack_o: out std_logic;
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a_ack_oi: in std_logic := '-';
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a_err_o: out std_logic;
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a_err_oi: in std_logic := '-';
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a_rty_o: out std_logic;
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a_rty_oi: in std_logic := '-';
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-- interface to master device b
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b_we_i: in std_logic;
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b_stb_i: in std_logic;
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b_cyc_i: in std_logic;
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b_ack_o: out std_logic;
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b_ack_oi: in std_logic := '-';
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b_err_o: out std_logic;
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b_err_oi: in std_logic := '-';
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b_rty_o: out std_logic;
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b_rty_oi: in std_logic := '-';
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-- interface to shared devices
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s_we_o: out std_logic;
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s_stb_o: out std_logic;
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
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-- misc control lines
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priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
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);
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end component;
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component wb_out_reg
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generic (
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reg_width : positive := 8;
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dat_width: positive := 8;
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offset: integer := 0
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_val: std_logic_vector(reg_width-1 downto 0) := (others => '0');
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cyc_i: in std_logic := '1';
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stb_i: in std_logic;
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sel_i: in std_logic_vector (max2((dat_width/8)-1,0) downto 0) := (others => '1');
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we_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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adr_i: in std_logic_vector (size2bits((reg_width+offset+dat_width-1)/dat_width)-1 downto 0) := (others => '0');
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dat_i: in std_logic_vector (dat_width-1 downto 0);
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dat_oi: in std_logic_vector (dat_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (dat_width-1 downto 0);
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q: out std_logic_vector (reg_width-1 downto 0)
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);
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end component;
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component wb_in_reg
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generic (
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reg_width : positive := 8;
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dat_width: positive := 8;
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offset: integer := 0
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic;
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cyc_i: in std_logic := '1';
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stb_i: in std_logic;
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sel_i: in std_logic_vector (max2((dat_width/8)-1,0) downto 0) := (others => '1');
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we_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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adr_i: in std_logic_vector (size2bits((reg_width+offset+dat_width-1)/dat_width)-1 downto 0) := (others => '0');
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dat_oi: in std_logic_vector (dat_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (dat_width-1 downto 0);
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i: in std_logic_vector (reg_width-1 downto 0)
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);
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end component;
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component wb_ram
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generic (
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dat_width: positive := 8;
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adr_width: positive := 10
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);
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port (
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clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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adr_i: in std_logic_vector (adr_width-1 downto 0);
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-- sel_i: in std_logic_vector ((dat_width/8)-1 downto 0) := (others => '1');
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dat_i: in std_logic_vector (dat_width-1 downto 0);
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dat_oi: in std_logic_vector (dat_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (dat_width-1 downto 0);
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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-- err_o: out std_logic;
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-- err_oi: in std_logic := '-';
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-- rty_o: out std_logic;
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-- rty_oi: in std_logic := '-';
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we_i: in std_logic;
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stb_i: in std_logic
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);
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end component;
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end components;
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