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--
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-- Technology mapping library. ALTERA edition.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library exemplar;
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--use exemplar.exemplar_1164.all;
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library synopsys;
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--use synopsys.std_logic_arith.all;
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package body technology is
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function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
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begin
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return std_logic_arith.CONV_STD_LOGIC_VECTOR(arg,size);
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end;
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function to_integer(arg:std_logic_vector) return integer is
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begin
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return CONV_INTEGER(arg);
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end;
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-- function "+"(op_l, op_r: std_logic_vector) return std_logic_vector is
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-- begin
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-- return exemplar_1164."+"(op_l, op_r);
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-- end;
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--
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-- function "-"(op_l, op_r: std_logic_vector) return std_logic_vector is
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-- begin
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-- return exemplar_1164."-"(op_l, op_r);
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-- end;
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--
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-- function add_one(inp : std_logic_vector) return std_logic_vector is
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-- variable one: std_logic_vector(inp'RANGE) := (others => '0');
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-- begin
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-- one(0) := '1';
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-- return exemplar_1164."+"(inp,one);
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-- end;
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--
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-- function sub_one(inp : std_logic_vector) return std_logic_vector is
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-- variable minus_one: std_logic_vector(inp'RANGE) := (others => '1');
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-- begin
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-- return exemplar_1164."+"(inp,minus_one);
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-- end;
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function is_zero(inp : std_logic_vector) return boolean is
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variable zero: std_logic_vector(inp'RANGE) := (others => '0');
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begin
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return (inp = zero);
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end;
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function sl(l: std_logic_vector; r: integer) return std_logic_vector is
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begin
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return exemplar_1164.sl(l,r);
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end;
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function sr(l: std_logic_vector; r: integer) return std_logic_vector is
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begin
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return sl(l,-r);
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end function;
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function max2(a : integer; b: integer) return integer is
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begin
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if (a > b) then return a; end if;
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return b;
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end;
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function min2(a : integer; b: integer) return integer is
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begin
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if (a < b) then return a; end if;
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return b;
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end;
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function log2(inp : integer) return integer is
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begin
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if (inp < 1) then return 0; end if;
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if (inp < 2) then return 0; end if;
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if (inp < 4) then return 1; end if;
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if (inp < 8) then return 2; end if;
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if (inp < 16) then return 3; end if;
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if (inp < 32) then return 4; end if;
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if (inp < 64) then return 5; end if;
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if (inp < 128) then return 6; end if;
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if (inp < 256) then return 7; end if;
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if (inp < 512) then return 8; end if;
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if (inp < 1024) then return 9; end if;
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if (inp < 2048) then return 10; end if;
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if (inp < 4096) then return 11; end if;
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if (inp < 8192) then return 12; end if;
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if (inp < 16384) then return 13; end if;
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if (inp < 32768) then return 14; end if;
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if (inp < 65536) then return 15; end if;
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return 16;
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end;
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function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer is
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begin
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if (in_bus = out_bus) then return 0; end if;
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if (in_bus < out_bus) then return -log2(out_bus/in_bus); end if;
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if (in_bus > out_bus) then return log2(in_bus/out_bus); end if;
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end;
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function size2bits(inp : integer) return integer is
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begin
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if (inp <= 1) then return 1; end if;
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if (inp <= 2) then return 1; end if;
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if (inp <= 4) then return 2; end if;
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if (inp <= 8) then return 3; end if;
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if (inp <= 16) then return 4; end if;
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if (inp <= 32) then return 5; end if;
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if (inp <= 64) then return 6; end if;
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if (inp <= 128) then return 7; end if;
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if (inp <= 256) then return 8; end if;
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if (inp <= 512) then return 9; end if;
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if (inp <= 1024) then return 10; end if;
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if (inp <= 2048) then return 11; end if;
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if (inp <= 4096) then return 12; end if;
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if (inp <= 8192) then return 13; end if;
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if (inp <= 16384) then return 14; end if;
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if (inp <= 32768) then return 15; end if;
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if (inp <= 65536) then return 16; end if;
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return 17;
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end;
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function equ(a : std_logic_vector; b : integer) return boolean is
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variable b_s : std_logic_vector(a'RANGE);
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begin
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b_s := to_std_logic_vector(b,a'HIGH+1);
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return (a = b_s);
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end;
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end package body technology;
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library IEEE;
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use IEEE.std_logic_1164.all;
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library altera;
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use altera.maxplus2.all;
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library alt_vtl;
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use alt_vtl.all;
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architecture altera of d_ff is
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signal clrn,prn: std_logic;
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begin
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clrn <= not clr;
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prn <= not pre;
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ff: dffe port map (
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D => d,
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CLK => clk,
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ENA => ena,
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CLRN => clrn,
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PRN => prn,
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Q => q
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);
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end altera;
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library ieee;
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use ieee.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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library lpm;
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use lpm.all;
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-- GENERIC usage
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-------------------
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-- default_out : Not used in altera implementation
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-- default_content : Not used in altera implementation
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-- adr_width : Correctly used
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-- dat_width : Correctly used
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-- async_read : Correctly used
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architecture altera of dpmem is
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signal wren, rden: std_logic;
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COMPONENT lpm_ram_dp
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generic (LPM_WIDTH : positive;
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LPM_WIDTHAD : positive;
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LPM_NUMWORDS : natural := 0;
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LPM_INDATA : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_RDADDRESS_CONTROL : string := "REGISTERED";
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LPM_WRADDRESS_CONTROL : string := "REGISTERED";
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LPM_FILE : string := "UNUSED";
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LPM_TYPE : string := "LPM_RAM_DP";
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LPM_HINT : string := "UNUSED"
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);
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port (RDCLOCK : in std_logic := '0';
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RDCLKEN : in std_logic := '1';
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RDADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
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RDEN : in std_logic := '1';
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DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
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WRADDRESS : in std_logic_vector(LPM_WIDTHad-1 downto 0);
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WREN : in std_logic;
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WRCLOCK : in std_logic := '0';
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WRCLKEN : in std_logic := '1';
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Q : out std_logic_vector(LPM_WIDTH-1 downto 0)
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);
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END COMPONENT;
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begin
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wren <= w_we_i and w_stb_i;
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rden <= not r_we_i and r_stb_i;
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w_ack_o <= '1'; -- 0-wait-state for writes
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r_ack_o <= '1'; -- 0-wait-state for reads
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sync_gen: if (not async_read) generate
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mem_core: lpm_ram_dp
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GENERIC MAP (
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lpm_width => dat_width,
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lpm_widthad => adr_width,
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lpm_indata => "REGISTERED",
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lpm_wraddress_control => "REGISTERED",
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lpm_rdaddress_control => "REGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_hint => "USE_EAB=ON"
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)
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PORT MAP (
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rdclock => r_clk_i,
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wren => wren,
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wrclock => w_clk_i,
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q => r_dat_o,
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rden => rden,
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data => w_dat_i,
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rdaddress => r_adr_i,
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wraddress => w_adr_i
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);
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end generate;
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async_gen: if (async_read) generate
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mem_core: lpm_ram_dp
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GENERIC MAP (
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lpm_width => dat_width,
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lpm_widthad => adr_width,
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lpm_indata => "REGISTERED",
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lpm_wraddress_control => "REGISTERED",
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lpm_rdaddress_control => "UNREGISTERED",
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lpm_outdata => "UNREGISTERED",
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lpm_hint => "USE_EAB=ON"
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)
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PORT MAP (
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rdclock => r_clk_i,
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wren => wren,
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wrclock => w_clk_i,
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q => r_dat_o,
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rden => rden,
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data => w_dat_i,
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rdaddress => r_adr_i,
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wraddress => w_adr_i
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);
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end generate;
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end altera;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library wb_tk;
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use wb_tk.technology.all;
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architecture altera of fifo is
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-- One additional bit is added to detect over and under-flow
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signal w_adr : std_logic_vector(adr_width downto 0); -- internal write address
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signal r_adr : std_logic_vector(adr_width downto 0); -- internal read address
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begin
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read_proc : process (r_clk_i, reset)
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begin
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if reset = '1' then
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r_adr <= (others => '0');
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elsif r_clk_i'event and r_clk_i = '1' then
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if (r_stb_i = '1' and r_we_i = '0') then
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r_adr <= r_adr+"1";
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end if;
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end if;
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end process read_proc;
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write_proc : process (w_clk_i, reset)
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begin
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if reset = '1' then
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w_adr <= (others => '0');
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elsif w_clk_i'event and w_clk_i = '1' then
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if (w_stb_i = '1' and w_we_i = '1') then
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w_adr <= w_adr+"1";
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end if;
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end if;
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end process write_proc;
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empty_o <= '1' when r_adr = w_adr else '0';
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full_o <= '1' when (w_adr(adr_width-1 downto 0) = r_adr(adr_width-1 downto 0)) and (w_adr(adr_width) /= r_adr(adr_width)) else '0';
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used_o <= w_adr - r_adr;
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mem_core: dpmem
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generic map (default_out,default_content,adr_width,dat_width,async_read)
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port map (
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-- signals for the read port
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r_clk_i => r_clk_i,
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r_stb_i => r_stb_i,
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r_we_i => r_we_i,
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r_adr_i => r_adr(adr_width-1 downto 0),
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r_dat_o => r_dat_o,
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r_ack_o => r_ack_o,
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-- signals for the write port
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w_clk_i => w_clk_i,
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w_stb_i => w_stb_i,
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w_we_i => w_we_i,
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w_adr_i => w_adr(adr_width-1 downto 0),
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w_dat_i => w_dat_i,
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w_ack_o => w_ack_o
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);
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end altera;
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library ieee;
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use ieee.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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architecture altera of spmem is
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signal r_ack: std_logic;
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signal w_ack: std_logic;
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begin
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mem_core: dpmem generic map (default_out,default_content,adr_width,dat_width,async_read)
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port map(
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-- Signals for the read port
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clk_i,
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stb_i,
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we_i,
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adr_i,
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dat_o,
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r_ack,
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-- Signals for the write port
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clk_i,
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stb_i,
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we_i,
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adr_i,
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dat_i,
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w_ack
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);
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ack_o <= '1';
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end altera;
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No newline at end of file
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No newline at end of file
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