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--
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-- Wishbone bus toolkit.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus
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-------------------------------------------------------------------------------
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--
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-- wb_arbiter
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity wb_arbiter is
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port (
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-- clk: in std_logic;
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rst_i: in std_logic := '0';
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-- interface to master device a
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a_we_i: in std_logic;
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a_stb_i: in std_logic;
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a_cyc_i: in std_logic;
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a_ack_o: out std_logic;
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a_ack_oi: in std_logic := '-';
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a_err_o: out std_logic;
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a_err_oi: in std_logic := '-';
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a_rty_o: out std_logic;
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a_rty_oi: in std_logic := '-';
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-- interface to master device b
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b_we_i: in std_logic;
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b_stb_i: in std_logic;
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b_cyc_i: in std_logic;
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b_ack_o: out std_logic;
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b_ack_oi: in std_logic := '-';
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b_err_o: out std_logic;
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b_err_oi: in std_logic := '-';
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b_rty_o: out std_logic;
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b_rty_oi: in std_logic := '-';
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-- interface to shared devices
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s_we_o: out std_logic;
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s_stb_o: out std_logic;
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
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-- misc control lines
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priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
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);
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end wb_arbiter;
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-- This acthitecture is a clean asyncron state-machine. However it cannot be mapped to FPGA architecture
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architecture behaviour of wb_arbiter is
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type states is (idle,aa,ba);
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signal i_mux_signal: std_logic;
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signal e_state: states;
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begin
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mux_signal <= i_mux_signal;
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sm: process
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variable state: states;
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begin
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wait on a_cyc_i, b_cyc_i, priority, rst_i;
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if (rst_i = '1') then
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state := idle;
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i_mux_signal <= priority;
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else
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case (state) is
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when idle =>
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if (a_cyc_i = '1' and (priority = '0' or b_cyc_i = '0')) then
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state := aa;
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i_mux_signal <= '0';
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elsif (b_cyc_i = '1' and (priority = '1' or a_cyc_i = '0')) then
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state := ba;
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i_mux_signal <= '1';
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else
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i_mux_signal <= priority;
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end if;
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when aa =>
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if (a_cyc_i = '0') then
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if (b_cyc_i = '1') then
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state := ba;
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i_mux_signal <= '1';
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else
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state := idle;
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i_mux_signal <= priority;
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end if;
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else
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i_mux_signal <= '0';
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end if;
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when ba =>
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if (b_cyc_i = '0') then
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if (a_cyc_i = '1') then
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state := aa;
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i_mux_signal <= '0';
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else
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state := idle;
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i_mux_signal <= priority;
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end if;
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else
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i_mux_signal <= '1';
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end if;
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end case;
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end if;
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e_state <= state;
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end process;
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signal_mux: process
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begin
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wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
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b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
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s_ack_i, s_err_i, s_rty_i, i_mux_signal;
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if (i_mux_signal = '0') then
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s_we_o <= a_we_i;
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s_stb_o <= a_stb_i;
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s_cyc_o <= a_cyc_i;
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a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
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a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
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a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
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b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
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b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
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b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
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else
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s_we_o <= b_we_i;
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s_stb_o <= b_stb_i;
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s_cyc_o <= b_cyc_i;
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b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
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b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
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b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
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a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
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a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
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a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
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end if;
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end process;
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end behaviour;
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-- This acthitecture is a more-or-less structural implementation. Fits for FPGA realization.
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architecture FPGA of wb_arbiter is
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component d_ff
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port ( d : in STD_LOGIC;
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clk: in STD_LOGIC;
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ena: in STD_LOGIC := '1';
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clr: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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q : out STD_LOGIC
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);
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end component;
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signal i_mux_signal: std_logic;
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type states is (idle,aa,ba,XX);
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signal e_state: states;
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-- signals for a DFF in FPGA
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signal idle_s, aa_s, ba_s: std_logic;
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signal aa_clk, aa_ena, aa_clr, aa_pre: std_logic;
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signal ba_clk, ba_ena, ba_clr, ba_pre: std_logic;
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signal one: std_logic := '1';
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begin
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one <= '1';
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mux_signal <= i_mux_signal;
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idle_s <= not (a_cyc_i or b_cyc_i);
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aa_clr <= rst_i or not a_cyc_i;
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aa_clk <= a_cyc_i;
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aa_ena <= not b_cyc_i and priority;
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aa_pre <= (a_cyc_i and not priority and not ba_s) or (a_cyc_i and not b_cyc_i);
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aa_ff: d_ff port map (
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d => one,
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clk => aa_clk,
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ena => aa_ena,
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clr => aa_clr,
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pre => aa_pre,
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q => aa_s
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);
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ba_clr <= rst_i or not b_cyc_i;
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ba_clk <= b_cyc_i;
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ba_ena <= not a_cyc_i and not priority;
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ba_pre <= (b_cyc_i and priority and not aa_s) or (b_cyc_i and not a_cyc_i);
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ba_ff: d_ff port map (
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d => one,
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clk => ba_clk,
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ena => ba_ena,
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clr => ba_clr,
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pre => ba_pre,
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q => ba_s
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);
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i_mux_signal <= (priority and idle_s) or ba_s;
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signal_mux: process
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begin
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wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
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b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
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s_ack_i, s_err_i, s_rty_i, i_mux_signal;
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if (i_mux_signal = '0') then
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s_we_o <= a_we_i;
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s_stb_o <= a_stb_i;
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s_cyc_o <= a_cyc_i;
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a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
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a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
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a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
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b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
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b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
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b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
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else
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s_we_o <= b_we_i;
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s_stb_o <= b_stb_i;
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s_cyc_o <= b_cyc_i;
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b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
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b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
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b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
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a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
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a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
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a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
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end if;
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end process;
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gen_e_state: process
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begin
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wait on idle_s,aa_s,ba_s;
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if (idle_s = '1' and ba_s = '0' and aa_s = '0') then e_state <= idle;
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elsif (idle_s = '0' and ba_s = '1' and aa_s = '0') then e_state <= aa;
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elsif (idle_s = '0' and ba_s = '0' and aa_s = '1') then e_state <= ba;
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else e_state <= XX;
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end if;
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end process;
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end FPGA;
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