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--
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-- Wishbone bus toolkit.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- wb_bus_dnsize: bus downsizer.
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-- doesn't split access cycles so granularity on the input bus must not be greater than
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-- the width of the output bus.
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-------------------------------------------------------------------------------
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--
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-- wb_bus_upsize
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity wb_bus_dnsize is
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generic (
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m_dat_width: positive := 32; -- master bus width
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m_adr_width: positive := 20; -- master bus width
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s_dat_width: positive := 16; -- slave bus width
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s_adr_width: positive := 21; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end wb_bus_dnsize;
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architecture wb_bus_dnsize of wb_bus_dnsize is
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constant addr_diff: integer := log2(m_dat_width/s_dat_width);
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constant mux_mask: integer := ((m_dat_width / 8)-1) - ((s_dat_width/8)-1);
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signal i_m_dat_o: std_logic_vector(m_dat_width-1 downto 0);
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signal mux_sel: std_logic_vector(log2(m_sel_i'HIGH+1)-1 downto 0);
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signal i_mux_sel: integer := 0;
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function prior_decode(inp: std_logic_vector) return integer is
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begin
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-- variable ret: std_logic_vector(log2(inp'HIGH)-1 downto 0) := (others = '1');
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for i in inp'HIGH downto 0 loop
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if (inp(i) = '1') then
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return i;
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end if;
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end loop;
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return inp'HIGH;
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end;
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begin
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assert (s_adr_width = m_adr_width+addr_diff) report "Address widths are not consistent" severity FAILURE;
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-- Reconstructing address bits (mux_sel)
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compute_mux_sel: process(m_sel_i)
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variable i: integer;
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begin
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-- wait on m_sel_i;
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i := prior_decode(m_sel_i);
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mux_sel <= to_std_logic_vector(i,log2(m_sel_i'HIGH+1)) and to_std_logic_vector(mux_mask,log2(m_sel_i'HIGH+1));
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end process;
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i_mux_sel <= to_integer(mux_sel);
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-- create slave address bus
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s_adr_o(s_adr_width-1 downto addr_diff) <= m_adr_i;
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s_adr_o_gen: process
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variable all_ones: std_logic_vector(addr_diff-1 downto 0) := (others => '1');
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begin
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--:::TA This does not work under webpack. Re-simulate!!!!
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-- wait on mux_sel(mux_sel'HIGH downto mux_sel'HIGH-addr_diff+1);
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wait on mux_sel;
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if (little_endien) then
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s_adr_o(addr_diff-1 downto 0) <= mux_sel(mux_sel'HIGH downto mux_sel'HIGH-addr_diff+1);
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else
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s_adr_o(addr_diff-1 downto 0) <= all_ones-mux_sel(mux_sel'HIGH downto mux_sel'HIGH-addr_diff+1);
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end if;
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end process;
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-- create output byte select signals
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s_sel_o <= m_sel_i(i_mux_sel+(s_dat_width/8)-1 downto i_mux_sel);
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s_we_o <= m_we_i;
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m_ack_o <= (m_stb_i and s_ack_i) or (not m_stb_i and m_ack_oi);
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m_err_o <= (m_stb_i and s_err_i) or (not m_stb_i and m_err_oi);
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m_rty_o <= (m_stb_i and s_rty_i) or (not m_stb_i and m_rty_oi);
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s_stb_o <= m_stb_i;
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s_cyc_o <= m_cyc_i;
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-- Multiplex data-bus down to the slave width
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s_dat_o <= m_dat_i((i_mux_sel)*8-1+s_dat_width downto (i_mux_sel)*8);
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m_dat_o_mux: process
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begin
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wait on m_dat_oi, s_dat_i, i_mux_sel, m_stb_i, m_we_i;
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m_dat_o <= m_dat_oi;
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if (m_stb_i = '1' and m_we_i = '0') then
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m_dat_o((i_mux_sel)*8-1+s_dat_width downto (i_mux_sel)*8) <= s_dat_i;
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end if;
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end process;
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end wb_bus_dnsize;
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