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--
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-- Wishbone bus toolkit.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- wb_bus_resize: bus resizer.
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-------------------------------------------------------------------------------
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--
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-- wb_bus_resize
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity wb_bus_resize is
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generic (
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m_dat_width: positive := 32; -- master bus width
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m_adr_width: positive := 19; -- master bus width
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s_dat_width: positive := 16; -- slave bus width
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s_adr_width: positive := 20; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end wb_bus_resize;
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architecture wb_bus_resize of wb_bus_resize is
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component wb_bus_upsize
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generic (
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m_dat_width: positive := 8; -- master bus width
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m_adr_width: positive := 21; -- master bus width
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s_dat_width: positive := 16; -- slave bus width
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s_adr_width: positive := 20; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end component;
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component wb_bus_dnsize
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generic (
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m_dat_width: positive := 32; -- master bus width
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m_adr_width: positive := 20; -- master bus width
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s_dat_width: positive := 16; -- slave bus width
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s_adr_width: positive := 21; -- master bus width
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_adr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_dat_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_dat_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_dat_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_dat_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_adr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_dat_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_dat_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_dat_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end component;
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begin
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dn_sel: if (m_dat_width > s_dat_width) generate
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dnsizer: wb_bus_dnsize
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generic map (
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m_dat_width => m_dat_width,
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m_adr_width => m_adr_width,
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s_dat_width => s_dat_width,
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s_adr_width => s_adr_width,
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little_endien => little_endien
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)
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port map
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(m_adr_i => m_adr_i,
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m_sel_i => m_sel_i,
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m_dat_i => m_dat_i,
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m_dat_oi => m_dat_oi,
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m_dat_o => m_dat_o,
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m_cyc_i => m_cyc_i,
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m_ack_o => m_ack_o,
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m_ack_oi => m_ack_oi,
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m_err_o => m_err_o,
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m_err_oi => m_err_oi,
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m_rty_o => m_rty_o,
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m_rty_oi => m_rty_oi,
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m_we_i => m_we_i,
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m_stb_i => m_stb_i,
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s_adr_o => s_adr_o,
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s_sel_o => s_sel_o,
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s_dat_i => s_dat_i,
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s_dat_o => s_dat_o,
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s_cyc_o => s_cyc_o,
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s_ack_i => s_ack_i,
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s_err_i => s_err_i,
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s_rty_i => s_rty_i,
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s_we_o => s_we_o,
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s_stb_o => s_stb_o
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);
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end generate;
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up_sel: if (m_dat_width < s_dat_width) generate
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upsizer: wb_bus_upsize
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generic map (
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m_dat_width => m_dat_width,
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m_adr_width => m_adr_width,
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s_dat_width => s_dat_width,
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s_adr_width => s_adr_width,
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little_endien => little_endien
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)
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port map
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(m_adr_i => m_adr_i,
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m_sel_i => m_sel_i,
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m_dat_i => m_dat_i,
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m_dat_oi => m_dat_oi,
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m_dat_o => m_dat_o,
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m_cyc_i => m_cyc_i,
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m_ack_o => m_ack_o,
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m_ack_oi => m_ack_oi,
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m_err_o => m_err_o,
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m_err_oi => m_err_oi,
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m_rty_o => m_rty_o,
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m_rty_oi => m_rty_oi,
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m_we_i => m_we_i,
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m_stb_i => m_stb_i,
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s_adr_o => s_adr_o,
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s_sel_o => s_sel_o,
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s_dat_i => s_dat_i,
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s_dat_o => s_dat_o,
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s_cyc_o => s_cyc_o,
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s_ack_i => s_ack_i,
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s_err_i => s_err_i,
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s_rty_i => s_rty_i,
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s_we_o => s_we_o,
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s_stb_o => s_stb_o
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);
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end generate;
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eq_sel: if (m_dat_width = s_dat_width) generate
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dat_o_for: for i in m_dat_o'RANGE generate
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dat_o_gen: m_dat_o(i) <= (s_dat_i(i) and m_stb_i and not m_we_i) or (m_dat_oi(i) and not (m_stb_i and not m_we_i));
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end generate;
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m_ack_o <= (s_ack_i and m_stb_i and not m_we_i) or (m_ack_oi and not (m_stb_i and not m_we_i));
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m_err_o <= (s_err_i and m_stb_i and not m_we_i) or (m_err_oi and not (m_stb_i and not m_we_i));
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m_rty_o <= (s_rty_i and m_stb_i and not m_we_i) or (m_rty_oi and not (m_stb_i and not m_we_i));
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s_adr_o <= m_adr_i;
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s_sel_o <= m_sel_i;
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s_dat_o <= m_dat_i;
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s_cyc_o <= m_cyc_i;
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s_we_o <= m_we_i;
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s_stb_o <= m_stb_i;
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end generate;
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end wb_bus_resize;
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