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--
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-- Wishbone bus toolkit.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- wb_out_reg: Wishbone bus compatible output register.
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-------------------------------------------------------------------------------
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--
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-- wb_out_reg
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity wb_out_reg is
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generic (
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reg_width : positive := 8;
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dat_width: positive := 8;
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offset: integer := 0
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_val: std_logic_vector(reg_width-1 downto 0) := (others => '0');
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cyc_i: in std_logic := '1';
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stb_i: in std_logic;
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sel_i: in std_logic_vector (max2((dat_width/8)-1,0) downto 0) := (others => '1');
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we_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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adr_i: in std_logic_vector (size2bits((reg_width+offset+dat_width-1)/dat_width)-1 downto 0) := (others => '0');
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dat_i: in std_logic_vector (dat_width-1 downto 0);
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dat_oi: in std_logic_vector (dat_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (dat_width-1 downto 0);
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q: out std_logic_vector (reg_width-1 downto 0)
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);
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end wb_out_reg;
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architecture wb_out_reg of wb_out_reg is
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signal content : std_logic_vector (reg_width-1 downto 0);
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signal word_en: std_logic_vector ((reg_width / dat_width)-1 downto 0);
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begin
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-- address demux
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adr_demux: process (adr_i)
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begin
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word_en <= (others => '0');
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word_en(to_integer(adr_i)) <= '1';
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end process;
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-- output bus handling with logic
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gen_dat_o: process(
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dat_oi, we_i, stb_i, content, word_en, cyc_i, sel_i
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)
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variable rd_sel: std_logic;
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variable dat_idx: integer;
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begin
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rd_sel := cyc_i and stb_i and not we_i;
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-- The default is the input, we'll override it if we need to
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for i in dat_o'RANGE loop
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dat_o(i) <= dat_oi(i);
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end loop;
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for i in content'RANGE loop
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dat_idx := (i+offset) mod dat_width;
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if (
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-- (sel_i((i/8) mod (dat_width/8)) = '1') and
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(word_en(i/dat_width) = '1') and
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(rd_sel = '1')
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) then
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-- dat_o(dat_idx) <= (dat_oi(dat_idx) and not rd_sel) or (content(i) and rd_sel);
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dat_o(dat_idx) <= content(i);
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end if;
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end loop;
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end process;
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-- dat_o <= dat_oi;
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-- this item never generates any wait-states
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ack_o <= stb_i or ack_oi;
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reg: process
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variable dat_idx: integer;
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begin
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wait until clk_i'EVENT and clk_i='1';
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if (rst_i = '1') then
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content <= rst_val;
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else
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if (stb_i = '1' and cyc_i = '1' and we_i = '1') then
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for i in content'RANGE loop
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dat_idx := (i+offset) mod dat_width;
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if (
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-- (sel_i((i/8) mod (dat_width/8)) = '1') and
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(word_en(i/dat_width) = '1')
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) then
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content(i) <= dat_i(dat_idx);
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end if;
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end loop;
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end if;
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end if;
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end process;
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q <= content;
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end wb_out_reg;
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