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--
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-- Wishbone bus tester utilities.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/17
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- procedure wr_chk_val: writes a value, reads it back an checks if it's the same
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-- procedure wr_val: writes a value
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-- procedure rd_val: reads a value
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-- procedure chk_val: checks (after read) a value
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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package wb_test is
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procedure wr_chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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constant data: in STD_LOGIC_VECTOR
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);
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procedure wr_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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constant data: in STD_LOGIC_VECTOR
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);
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procedure rd_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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variable data: out STD_LOGIC_VECTOR
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);
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procedure chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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constant data: in STD_LOGIC_VECTOR
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);
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procedure wr_chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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constant data: in STD_LOGIC_VECTOR
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);
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procedure wr_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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constant data: in STD_LOGIC_VECTOR
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);
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procedure rd_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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variable data: out STD_LOGIC_VECTOR
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);
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procedure chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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constant data: in STD_LOGIC_VECTOR
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);
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end wb_test;
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package body wb_test is
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procedure wr_chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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constant data: in STD_LOGIC_VECTOR
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) is
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variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
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variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
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begin
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adr_i <= adr_zero;
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dat_i <= dat_undef;
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stb_i <= '0';
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we_i <= '0';
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cyc_i <= '0';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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adr_i <= addr;
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dat_i <= data;
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cyc_i <= '1';
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stb_i <= '1';
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we_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
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adr_i <= adr_zero;
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dat_i <= dat_undef;
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cyc_i <= '0';
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stb_i <= '0';
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we_i <= '0';
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wait until clk_i'EVENT and clk_i = '1';
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adr_i <= addr;
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dat_i <= dat_undef;
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cyc_i <= '1';
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stb_i <= '1';
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we_i <= '0';
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wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
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assert dat_o = data report "Value does not match!" severity ERROR;
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adr_i <= adr_zero;
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stb_i <= '0';
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cyc_i <= '0';
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end;
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procedure wr_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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constant data: in STD_LOGIC_VECTOR
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) is
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variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
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variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
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begin
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adr_i <= adr_zero;
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dat_i <= dat_undef;
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stb_i <= '0';
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we_i <= '0';
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cyc_i <= '0';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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adr_i <= addr;
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dat_i <= data;
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cyc_i <= '1';
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stb_i <= '1';
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we_i <= '1';
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wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
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adr_i <= adr_zero;
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dat_i <= dat_undef;
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cyc_i <= '0';
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stb_i <= '0';
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we_i <= '0';
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end;
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procedure rd_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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variable data: out STD_LOGIC_VECTOR
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) is
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variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
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variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
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begin
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adr_i <= adr_zero;
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dat_i <= dat_undef;
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cyc_i <= '0';
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stb_i <= '0';
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we_i <= '0';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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adr_i <= addr;
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dat_i <= dat_undef;
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cyc_i <= '1';
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stb_i <= '1';
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we_i <= '0';
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wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
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data := dat_o;
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adr_i <= adr_zero;
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stb_i <= '0';
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cyc_i <= '0';
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end;
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procedure chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in STD_LOGIC_VECTOR;
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constant data: in STD_LOGIC_VECTOR
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) is
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variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
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variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
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begin
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adr_i <= adr_zero;
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dat_i <= dat_undef;
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cyc_i <= '0';
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stb_i <= '0';
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we_i <= '0';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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wait until clk_i'EVENT and clk_i = '1';
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adr_i <= addr;
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dat_i <= dat_undef;
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cyc_i <= '1';
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stb_i <= '1';
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we_i <= '0';
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wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
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assert dat_o = data report "Value does not match!" severity ERROR;
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adr_i <= adr_zero;
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stb_i <= '0';
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cyc_i <= '0';
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end;
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procedure wr_chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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constant data: in STD_LOGIC_VECTOR
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) is
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variable sadr: std_logic_vector(adr_i'RANGE);
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begin
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sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
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wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
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end;
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procedure wr_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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constant data: in STD_LOGIC_VECTOR
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) is
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variable sadr: std_logic_vector(adr_i'RANGE);
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begin
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sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
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wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
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end;
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procedure rd_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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variable data: out STD_LOGIC_VECTOR
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) is
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variable sadr: std_logic_vector(adr_i'RANGE);
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begin
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sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
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rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
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end;
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procedure chk_val(
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signal clk_i: in STD_LOGIC;
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signal adr_i: out STD_LOGIC_VECTOR;
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signal dat_o: in STD_LOGIC_VECTOR;
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signal dat_i: out STD_LOGIC_VECTOR;
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signal we_i: out STD_LOGIC;
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signal cyc_i: out std_logic;
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signal stb_i: out STD_LOGIC;
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signal ack_o: in STD_LOGIC;
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constant addr: in integer;
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constant data: in STD_LOGIC_VECTOR
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) is
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variable sadr: std_logic_vector(adr_i'RANGE);
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begin
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sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
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chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
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end;
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end wb_test;
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No newline at end of file
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