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https://opencores.org/ocsvn/wb_to_amba/wb_to_amba/trunk
[/] [wb_to_amba/] [trunk/] [src/] [wb_arm_phase_fsm.v] - Diff between revs 2 and 3
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`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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module wb_arm_phase_fsm(
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module
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wb_arm_phase_fsm(
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input ahb_hclk,
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input ahb_hclk,
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input ahb_hreset,
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input ahb_hreset,
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input ahb_hsel,
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input ahb_hsel,
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input ahb_hready_in,
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input ahb_hready_in,
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input ahb_hready_out,
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input ahb_hready_out,
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input [1:0] ahb_htrans,
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output ahb_data_phase,
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output ahb_data_phase,
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output fsm_error
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output fsm_error
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);
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);
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// -----------------------------
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// do_transfer if not IDLE or BUSY
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wire do_transfer = (ahb_htrans == 2'b10) | (ahb_htrans == 2'b11);
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// -----------------------------
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// -----------------------------
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// state machine binary definitions
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// state machine binary definitions
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parameter IDLE_STATE = 3'b001;
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parameter IDLE_STATE = 3'b001;
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parameter DATA_STATE = 3'b010;
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parameter DATA_STATE = 3'b010;
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// -----------------------------
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// -----------------------------
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// state machine
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// state machine
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always @(*)
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always @(*)
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case(state)
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case(state)
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IDLE_STATE: if( ahb_hsel & ahb_hready_in )
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IDLE_STATE: if( ahb_hsel & ahb_hready_in & do_transfer)
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next_state <= DATA_STATE;
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next_state <= DATA_STATE;
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else
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else
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next_state <= IDLE_STATE;
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next_state <= IDLE_STATE;
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DATA_STATE: if( ahb_hready_out )
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DATA_STATE: if( ahb_hready_out )
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// -----------------------------
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// -----------------------------
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// outputs
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// outputs
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assign ahb_data_phase = (state == DATA_STATE);
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assign ahb_data_phase = (state == DATA_STATE);
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assign fsm_error = (state == ERROR_STATE);
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assign fsm_error = (state == ERROR_STATE);
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endmodule
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endmodule
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