| Line 5... |
Line 5... |
`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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module
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module
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wb_arm_slave_top
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wb_arm_slave_top
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#(
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#(
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parameter AWIDTH = 8,
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parameter AWIDTH = 32,
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parameter DWIDTH = 32
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parameter DWIDTH = 32
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)
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)
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(
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(
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// -----------------------------
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// -----------------------------
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// AHB interface
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// AHB interface
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| Line 47... |
Line 47... |
output wb_rst_o // reset input
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output wb_rst_o // reset input
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);
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);
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// -----------------------------
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// -----------------------------
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// ahb_haddr & control flops
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// ahb_haddr & control flops
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wire flop_en = ahb_hready_in & ahb_hsel;
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wire flop_en = ahb_hready_in & ahb_hsel & ~ahb_data_phase;
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reg [AWIDTH-1:0] ahb_haddr_r;
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reg [AWIDTH-1:0] ahb_haddr_r;
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always @ (posedge ahb_hclk)
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always @ (posedge ahb_hclk)
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if ( flop_en )
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if ( flop_en )
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ahb_haddr_r <= ahb_haddr;
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ahb_haddr_r <= ahb_haddr;
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| Line 84... |
Line 84... |
// -----------------------------
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// -----------------------------
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// wb_arm_phase_fsm
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// wb_arm_phase_fsm
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wire ahb_data_phase;
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wire ahb_data_phase;
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wire fsm_error;
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wire fsm_error;
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wb_arm_phase_fsm i_wb_arm_phase_fsm(
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wb_arm_phase_fsm
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i_wb_arm_phase_fsm(
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.ahb_hclk (ahb_hclk),
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.ahb_hclk (ahb_hclk),
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.ahb_hreset (ahb_hreset),
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.ahb_hreset (ahb_hreset),
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.ahb_hsel (ahb_hsel),
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.ahb_hsel (ahb_hsel),
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.ahb_hready_in (ahb_hready_in),
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.ahb_hready_in (ahb_hready_in),
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.ahb_hready_out (ahb_hready_out),
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.ahb_hready_out (ahb_hready_out),
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.ahb_htrans (ahb_htrans),
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.ahb_data_phase (ahb_data_phase),
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.ahb_data_phase (ahb_data_phase),
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.fsm_error (fsm_error)
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.fsm_error (fsm_error)
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);
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);
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