--
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--
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-- Programmable sync generator.
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-- Programmable sync generator.
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--
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- Standard library.
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-- Standard library.
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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library work;
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library work;
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use work.technology.all;
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use work.technology.all;
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entity sync_gen is
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entity sync_gen is
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port (
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port (
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clk: in std_logic;
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clk: in std_logic;
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clk_en: in std_logic;
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clk_en: in std_logic;
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reset: in std_logic := '0';
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reset: in std_logic := '0';
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bs: in std_logic_vector(7 downto 0);
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bs: in std_logic_vector(7 downto 0);
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ss: in std_logic_vector(7 downto 0);
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ss: in std_logic_vector(7 downto 0);
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se: in std_logic_vector(7 downto 0);
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se: in std_logic_vector(7 downto 0);
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total: in std_logic_vector(7 downto 0);
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total: in std_logic_vector(7 downto 0);
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sync: out std_logic;
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sync: out std_logic;
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blank: out std_logic;
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blank: out std_logic;
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tc: out std_logic;
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tc: out std_logic;
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count: out std_logic_vector (7 downto 0)
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count: out std_logic_vector (7 downto 0)
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);
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);
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end sync_gen;
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end sync_gen;
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architecture sync_gen of sync_gen is
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architecture sync_gen of sync_gen is
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begin
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begin
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-- And the sequential machine generating the output signals.
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-- And the sequential machine generating the output signals.
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generator: process is
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generator: process is
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variable state: std_logic_vector(7 downto 0);
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variable state: std_logic_vector(7 downto 0);
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begin
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begin
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wait until clk'event and clk='1';
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wait until clk'event and clk='1';
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if (reset = '1') then
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if (reset = '1') then
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tc <= '0';
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tc <= '0';
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state := (others => '0');
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state := (others => '0');
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sync <= '0';
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sync <= '0';
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tc <= '0';
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tc <= '0';
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blank <= '1';
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blank <= '1';
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else
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else
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if (clk_en='1') then
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if (clk_en='1') then
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if (state = bs) then
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if (state = bs) then
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sync <= '0';
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sync <= '0';
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blank <= '1';
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blank <= '1';
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tc <= '0';
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tc <= '0';
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state := add_one(state);
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state := add_one(state);
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elsif (state = ss) then
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elsif (state = ss) then
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sync <= '1';
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sync <= '1';
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blank <= '1';
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blank <= '1';
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tc <= '1';
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tc <= '1';
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state := add_one(state);
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state := add_one(state);
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elsif (state = se) then
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elsif (state = se) then
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sync <= '0';
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sync <= '0';
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blank <= '1';
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blank <= '1';
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tc <= '0';
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tc <= '0';
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state := add_one(state);
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state := add_one(state);
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elsif (state = total) then
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elsif (state = total) then
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sync <= '0';
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sync <= '0';
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blank <= '0';
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blank <= '0';
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tc <= '0';
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tc <= '0';
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state := (others => '0');
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state := (others => '0');
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else
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else
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tc <= '0';
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tc <= '0';
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state := add_one(state);
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state := add_one(state);
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end if;
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end if;
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count <= state;
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count <= state;
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else
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else
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tc <= '0';
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tc <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end sync_gen;
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end sync_gen;
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