--
|
--
|
-- Wishbone bus toolkit.
|
-- Wishbone bus toolkit.
|
--
|
--
|
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
|
-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
|
-- This code is distributed under the terms and conditions of the GNU General Public Lince.
|
-- This code is distributed under the terms and conditions of the GNU General Public Lince.
|
--
|
--
|
--
|
--
|
-- ELEMENTS:
|
-- ELEMENTS:
|
-- wb_bus_upsize: bus upsizer. Currently only 8->16 bit bus resize is supported
|
-- wb_bus_upsize: bus upsizer. Currently only 8->16 bit bus resize is supported
|
-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.
|
-- wb_async_slave: Wishbone bus to async (SRAM-like) bus slave bridge.
|
-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus
|
-- wb_arbiter: two-way bus arbiter. Asyncronous logic ensures 0-ws operation on shared bus
|
-- wb_out_reg: Wishbone bus compatible output register.
|
-- wb_out_reg: Wishbone bus compatible output register.
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
package wb_tk is
|
package wb_tk is
|
component wb_bus_upsize is
|
component wb_bus_upsize is
|
generic (
|
generic (
|
m_bus_width: positive := 8; -- master bus width
|
m_bus_width: positive := 8; -- master bus width
|
m_addr_width: positive := 21; -- master bus width
|
m_addr_width: positive := 21; -- master bus width
|
s_bus_width: positive := 16; -- slave bus width
|
s_bus_width: positive := 16; -- slave bus width
|
s_addr_width: positive := 20; -- master bus width
|
s_addr_width: positive := 20; -- master bus width
|
little_endien: boolean := true -- if set to false, big endien
|
little_endien: boolean := true -- if set to false, big endien
|
);
|
);
|
port (
|
port (
|
-- clk_i: in std_logic;
|
-- clk_i: in std_logic;
|
-- rst_i: in std_logic := '0';
|
-- rst_i: in std_logic := '0';
|
|
|
-- Master bus interface
|
-- Master bus interface
|
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
|
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
|
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
|
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
|
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
|
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
|
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
|
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
|
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
|
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
|
m_cyc_i: in std_logic;
|
m_cyc_i: in std_logic;
|
m_ack_o: out std_logic;
|
m_ack_o: out std_logic;
|
m_ack_oi: in std_logic := '-';
|
m_ack_oi: in std_logic := '-';
|
m_err_o: out std_logic;
|
m_err_o: out std_logic;
|
m_err_oi: in std_logic := '-';
|
m_err_oi: in std_logic := '-';
|
m_rty_o: out std_logic;
|
m_rty_o: out std_logic;
|
m_rty_oi: in std_logic := '-';
|
m_rty_oi: in std_logic := '-';
|
m_we_i: in std_logic;
|
m_we_i: in std_logic;
|
m_stb_i: in std_logic;
|
m_stb_i: in std_logic;
|
|
|
-- Slave bus interface
|
-- Slave bus interface
|
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
|
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
|
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
|
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
|
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
|
s_cyc_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_ack_i: in std_logic;
|
s_ack_i: in std_logic;
|
s_err_i: in std_logic := '-';
|
s_err_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_we_o: out std_logic;
|
s_we_o: out std_logic;
|
s_stb_o: out std_logic
|
s_stb_o: out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component wb_async_master is
|
component wb_async_master is
|
generic (
|
generic (
|
width: positive := 16;
|
width: positive := 16;
|
addr_width: positive := 20
|
addr_width: positive := 20
|
);
|
);
|
port (
|
port (
|
clk_i: in std_logic;
|
clk_i: in std_logic;
|
rst_i: in std_logic := '0';
|
rst_i: in std_logic := '0';
|
|
|
-- interface to wb slave devices
|
-- interface to wb slave devices
|
s_adr_o: out std_logic_vector (addr_width-1 downto 0);
|
s_adr_o: out std_logic_vector (addr_width-1 downto 0);
|
s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
|
s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
|
s_dat_i: in std_logic_vector (width-1 downto 0);
|
s_dat_i: in std_logic_vector (width-1 downto 0);
|
s_dat_o: out std_logic_vector (width-1 downto 0);
|
s_dat_o: out std_logic_vector (width-1 downto 0);
|
s_cyc_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_ack_i: in std_logic;
|
s_ack_i: in std_logic;
|
s_err_i: in std_logic := '-';
|
s_err_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_we_o: out std_logic;
|
s_we_o: out std_logic;
|
s_stb_o: out std_logic;
|
s_stb_o: out std_logic;
|
|
|
-- interface to asyncron master device
|
-- interface to asyncron master device
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_rdn: in std_logic := '1';
|
a_rdn: in std_logic := '1';
|
a_wrn: in std_logic := '1';
|
a_wrn: in std_logic := '1';
|
a_cen: in std_logic := '1';
|
a_cen: in std_logic := '1';
|
a_byen: in std_logic_vector ((width/8)-1 downto 0);
|
a_byen: in std_logic_vector ((width/8)-1 downto 0);
|
a_waitn: out std_logic
|
a_waitn: out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
component wb_async_slave is
|
component wb_async_slave is
|
generic (
|
generic (
|
width: positive := 16;
|
width: positive := 16;
|
addr_width: positive := 20
|
addr_width: positive := 20
|
);
|
);
|
port (
|
port (
|
clk_i: in std_logic;
|
clk_i: in std_logic;
|
rst_i: in std_logic := '0';
|
rst_i: in std_logic := '0';
|
|
|
-- interface for wait-state generator state-machine
|
-- interface for wait-state generator state-machine
|
wait_state: in std_logic_vector (3 downto 0);
|
wait_state: in std_logic_vector (3 downto 0);
|
|
|
-- interface to wishbone master device
|
-- interface to wishbone master device
|
adr_i: in std_logic_vector (addr_width-1 downto 0);
|
adr_i: in std_logic_vector (addr_width-1 downto 0);
|
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
|
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
|
dat_i: in std_logic_vector (width-1 downto 0);
|
dat_i: in std_logic_vector (width-1 downto 0);
|
dat_o: out std_logic_vector (width-1 downto 0);
|
dat_o: out std_logic_vector (width-1 downto 0);
|
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
|
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
|
we_i: in std_logic;
|
we_i: in std_logic;
|
stb_i: in std_logic;
|
stb_i: in std_logic;
|
ack_o: out std_logic := '0';
|
ack_o: out std_logic := '0';
|
ack_oi: in std_logic := '-';
|
ack_oi: in std_logic := '-';
|
|
|
-- interface to async slave
|
-- interface to async slave
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_rdn: out std_logic := '1';
|
a_rdn: out std_logic := '1';
|
a_wrn: out std_logic := '1';
|
a_wrn: out std_logic := '1';
|
a_cen: out std_logic := '1';
|
a_cen: out std_logic := '1';
|
-- byte-enable signals
|
-- byte-enable signals
|
a_byen: out std_logic_vector ((width/8)-1 downto 0)
|
a_byen: out std_logic_vector ((width/8)-1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component wb_arbiter is
|
component wb_arbiter is
|
port (
|
port (
|
-- clk_i: in std_logic;
|
-- clk_i: in std_logic;
|
rst_i: in std_logic := '0';
|
rst_i: in std_logic := '0';
|
|
|
-- interface to master device a
|
-- interface to master device a
|
a_we_i: in std_logic;
|
a_we_i: in std_logic;
|
a_stb_i: in std_logic;
|
a_stb_i: in std_logic;
|
a_cyc_i: in std_logic;
|
a_cyc_i: in std_logic;
|
a_ack_o: out std_logic;
|
a_ack_o: out std_logic;
|
a_ack_oi: in std_logic := '-';
|
a_ack_oi: in std_logic := '-';
|
a_err_o: out std_logic;
|
a_err_o: out std_logic;
|
a_err_oi: in std_logic := '-';
|
a_err_oi: in std_logic := '-';
|
a_rty_o: out std_logic;
|
a_rty_o: out std_logic;
|
a_rty_oi: in std_logic := '-';
|
a_rty_oi: in std_logic := '-';
|
|
|
-- interface to master device b
|
-- interface to master device b
|
b_we_i: in std_logic;
|
b_we_i: in std_logic;
|
b_stb_i: in std_logic;
|
b_stb_i: in std_logic;
|
b_cyc_i: in std_logic;
|
b_cyc_i: in std_logic;
|
b_ack_o: out std_logic;
|
b_ack_o: out std_logic;
|
b_ack_oi: in std_logic := '-';
|
b_ack_oi: in std_logic := '-';
|
b_err_o: out std_logic;
|
b_err_o: out std_logic;
|
b_err_oi: in std_logic := '-';
|
b_err_oi: in std_logic := '-';
|
b_rty_o: out std_logic;
|
b_rty_o: out std_logic;
|
b_rty_oi: in std_logic := '-';
|
b_rty_oi: in std_logic := '-';
|
|
|
-- interface to shared devices
|
-- interface to shared devices
|
s_we_o: out std_logic;
|
s_we_o: out std_logic;
|
s_stb_o: out std_logic;
|
s_stb_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_ack_i: in std_logic;
|
s_ack_i: in std_logic;
|
s_err_i: in std_logic := '-';
|
s_err_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
|
|
mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
|
mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
|
|
|
-- misc control lines
|
-- misc control lines
|
priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
|
priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
|
);
|
);
|
end component;
|
end component;
|
|
|
component wb_out_reg is
|
component wb_out_reg is
|
generic (
|
generic (
|
width : positive := 8;
|
width : positive := 8;
|
bus_width: positive := 8;
|
bus_width: positive := 8;
|
offset: integer := 0
|
offset: integer := 0
|
);
|
);
|
port (
|
port (
|
clk_i: in std_logic;
|
clk_i: in std_logic;
|
rst_i: in std_logic;
|
rst_i: in std_logic;
|
rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
|
rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
|
|
|
dat_i: in std_logic_vector (bus_width-1 downto 0);
|
dat_i: in std_logic_vector (bus_width-1 downto 0);
|
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
|
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
|
dat_o: out std_logic_vector (bus_width-1 downto 0);
|
dat_o: out std_logic_vector (bus_width-1 downto 0);
|
q: out std_logic_vector (width-1 downto 0);
|
q: out std_logic_vector (width-1 downto 0);
|
we_i: in std_logic;
|
we_i: in std_logic;
|
stb_i: in std_logic;
|
stb_i: in std_logic;
|
ack_o: out std_logic;
|
ack_o: out std_logic;
|
ack_oi: in std_logic := '-'
|
ack_oi: in std_logic := '-'
|
);
|
);
|
end component;
|
end component;
|
end wb_tk;
|
end wb_tk;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- wb_bus_upsize
|
-- wb_bus_upsize
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
library synopsys;
|
library synopsys;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
use synopsys.std_logic_arith.all;
|
use synopsys.std_logic_arith.all;
|
|
|
library work;
|
library work;
|
use work.technology.all;
|
use work.technology.all;
|
|
|
entity wb_bus_upsize is
|
entity wb_bus_upsize is
|
generic (
|
generic (
|
m_bus_width: positive := 8; -- master bus width
|
m_bus_width: positive := 8; -- master bus width
|
m_addr_width: positive := 21; -- master bus width
|
m_addr_width: positive := 21; -- master bus width
|
s_bus_width: positive := 16; -- slave bus width
|
s_bus_width: positive := 16; -- slave bus width
|
s_addr_width: positive := 20; -- master bus width
|
s_addr_width: positive := 20; -- master bus width
|
little_endien: boolean := true -- if set to false, big endien
|
little_endien: boolean := true -- if set to false, big endien
|
);
|
);
|
port (
|
port (
|
-- clk_i: in std_logic;
|
-- clk_i: in std_logic;
|
-- rst_i: in std_logic := '0';
|
-- rst_i: in std_logic := '0';
|
|
|
-- Master bus interface
|
-- Master bus interface
|
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
|
m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
|
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
|
m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
|
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
|
m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
|
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
|
m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
|
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
|
m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
|
m_cyc_i: in std_logic;
|
m_cyc_i: in std_logic;
|
m_ack_o: out std_logic;
|
m_ack_o: out std_logic;
|
m_ack_oi: in std_logic := '-';
|
m_ack_oi: in std_logic := '-';
|
m_err_o: out std_logic;
|
m_err_o: out std_logic;
|
m_err_oi: in std_logic := '-';
|
m_err_oi: in std_logic := '-';
|
m_rty_o: out std_logic;
|
m_rty_o: out std_logic;
|
m_rty_oi: in std_logic := '-';
|
m_rty_oi: in std_logic := '-';
|
m_we_i: in std_logic;
|
m_we_i: in std_logic;
|
m_stb_i: in std_logic;
|
m_stb_i: in std_logic;
|
|
|
-- Slave bus interface
|
-- Slave bus interface
|
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
|
s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
|
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
|
s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
|
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
|
s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
|
s_cyc_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_ack_i: in std_logic;
|
s_ack_i: in std_logic;
|
s_err_i: in std_logic := '-';
|
s_err_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_we_o: out std_logic;
|
s_we_o: out std_logic;
|
s_stb_o: out std_logic
|
s_stb_o: out std_logic
|
);
|
);
|
end wb_bus_upsize;
|
end wb_bus_upsize;
|
|
|
architecture wb_bus_upsize of wb_bus_upsize is
|
architecture wb_bus_upsize of wb_bus_upsize is
|
function log2(inp : integer) return integer is
|
function log2(inp : integer) return integer is
|
begin
|
begin
|
if (inp < 1) then return 0; end if;
|
if (inp < 1) then return 0; end if;
|
if (inp < 2) then return 0; end if;
|
if (inp < 2) then return 0; end if;
|
if (inp < 4) then return 1; end if;
|
if (inp < 4) then return 1; end if;
|
if (inp < 8) then return 2; end if;
|
if (inp < 8) then return 2; end if;
|
if (inp < 16) then return 3; end if;
|
if (inp < 16) then return 3; end if;
|
if (inp < 32) then return 4; end if;
|
if (inp < 32) then return 4; end if;
|
if (inp < 64) then return 5; end if;
|
if (inp < 64) then return 5; end if;
|
if (inp < 128) then return 6; end if;
|
if (inp < 128) then return 6; end if;
|
if (inp < 256) then return 7; end if;
|
if (inp < 256) then return 7; end if;
|
if (inp < 512) then return 8; end if;
|
if (inp < 512) then return 8; end if;
|
if (inp < 1024) then return 9; end if;
|
if (inp < 1024) then return 9; end if;
|
if (inp < 2048) then return 10; end if;
|
if (inp < 2048) then return 10; end if;
|
if (inp < 4096) then return 11; end if;
|
if (inp < 4096) then return 11; end if;
|
if (inp < 8192) then return 12; end if;
|
if (inp < 8192) then return 12; end if;
|
if (inp < 16384) then return 13; end if;
|
if (inp < 16384) then return 13; end if;
|
if (inp < 32768) then return 14; end if;
|
if (inp < 32768) then return 14; end if;
|
if (inp < 65538) then return 15; end if;
|
if (inp < 65538) then return 15; end if;
|
return 16;
|
return 16;
|
end;
|
end;
|
function equ(a : std_logic_vector; b : integer) return boolean is
|
function equ(a : std_logic_vector; b : integer) return boolean is
|
variable b_s : std_logic_vector(a'RANGE);
|
variable b_s : std_logic_vector(a'RANGE);
|
begin
|
begin
|
b_s := CONV_STD_LOGIC_VECTOR(b,a'HIGH+1);
|
b_s := CONV_STD_LOGIC_VECTOR(b,a'HIGH+1);
|
return (a = b_s);
|
return (a = b_s);
|
end;
|
end;
|
constant addr_diff: integer := log2(s_bus_width/m_bus_width);
|
constant addr_diff: integer := log2(s_bus_width/m_bus_width);
|
signal i_m_dat_o: std_logic_vector(m_bus_width-1 downto 0);
|
signal i_m_dat_o: std_logic_vector(m_bus_width-1 downto 0);
|
begin
|
begin
|
assert (m_addr_width = s_addr_width+addr_diff) report "Address widths are not consistent" severity FAILURE;
|
assert (m_addr_width = s_addr_width+addr_diff) report "Address widths are not consistent" severity FAILURE;
|
s_adr_o <= m_adr_i(m_addr_width-addr_diff downto addr_diff);
|
s_adr_o <= m_adr_i(m_addr_width-addr_diff downto addr_diff);
|
s_we_o <= m_we_i;
|
s_we_o <= m_we_i;
|
m_ack_o <= (m_stb_i and s_ack_i) or (not m_stb_i and m_ack_oi);
|
m_ack_o <= (m_stb_i and s_ack_i) or (not m_stb_i and m_ack_oi);
|
m_err_o <= (m_stb_i and s_err_i) or (not m_stb_i and m_err_oi);
|
m_err_o <= (m_stb_i and s_err_i) or (not m_stb_i and m_err_oi);
|
m_rty_o <= (m_stb_i and s_rty_i) or (not m_stb_i and m_rty_oi);
|
m_rty_o <= (m_stb_i and s_rty_i) or (not m_stb_i and m_rty_oi);
|
s_stb_o <= m_stb_i;
|
s_stb_o <= m_stb_i;
|
s_cyc_o <= m_cyc_i;
|
s_cyc_o <= m_cyc_i;
|
|
|
|
|
sel_dat_mux: process is
|
sel_dat_mux: process is
|
begin
|
begin
|
wait on s_dat_i, m_adr_i;
|
wait on s_dat_i, m_adr_i;
|
if (little_endien) then
|
if (little_endien) then
|
for i in s_sel_o'RANGE loop
|
for i in s_sel_o'RANGE loop
|
if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
|
if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
|
s_sel_o(i) <= '1';
|
s_sel_o(i) <= '1';
|
i_m_dat_o <= s_dat_i(8*i+7 downto 8*i+0);
|
i_m_dat_o <= s_dat_i(8*i+7 downto 8*i+0);
|
else
|
else
|
s_sel_o(i) <= '0';
|
s_sel_o(i) <= '0';
|
end if;
|
end if;
|
end loop;
|
end loop;
|
else
|
else
|
for i in s_sel_o'RANGE loop
|
for i in s_sel_o'RANGE loop
|
if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
|
if (equ(m_adr_i(addr_diff-1 downto 0),i)) then
|
s_sel_o(s_sel_o'HIGH-i) <= '1';
|
s_sel_o(s_sel_o'HIGH-i) <= '1';
|
i_m_dat_o <= s_dat_i(s_dat_i'HIGH-8*i downto s_dat_i'HIGH-8*i-7);
|
i_m_dat_o <= s_dat_i(s_dat_i'HIGH-8*i downto s_dat_i'HIGH-8*i-7);
|
else
|
else
|
s_sel_o(s_sel_o'HIGH-i) <= '0';
|
s_sel_o(s_sel_o'HIGH-i) <= '0';
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
d_i_for: for i in m_dat_o'RANGE generate
|
d_i_for: for i in m_dat_o'RANGE generate
|
m_dat_o(i) <= (m_stb_i and i_m_dat_o(i)) or (not m_stb_i and m_dat_oi(i));
|
m_dat_o(i) <= (m_stb_i and i_m_dat_o(i)) or (not m_stb_i and m_dat_oi(i));
|
end generate;
|
end generate;
|
|
|
d_o_for: for i in s_sel_o'RANGE generate
|
d_o_for: for i in s_sel_o'RANGE generate
|
s_dat_o(8*i+7 downto 8*i+0) <= m_dat_i;
|
s_dat_o(8*i+7 downto 8*i+0) <= m_dat_i;
|
end generate;
|
end generate;
|
end wb_bus_upsize;
|
end wb_bus_upsize;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- wb_async_master
|
-- wb_async_master
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
library work;
|
library work;
|
use work.technology.all;
|
use work.technology.all;
|
|
|
entity wb_async_master is
|
entity wb_async_master is
|
generic (
|
generic (
|
width: positive := 16;
|
width: positive := 16;
|
addr_width: positive := 20
|
addr_width: positive := 20
|
);
|
);
|
port (
|
port (
|
clk_i: in std_logic;
|
clk_i: in std_logic;
|
rst_i: in std_logic := '0';
|
rst_i: in std_logic := '0';
|
|
|
-- interface to wb slave devices
|
-- interface to wb slave devices
|
s_adr_o: out std_logic_vector (addr_width-1 downto 0);
|
s_adr_o: out std_logic_vector (addr_width-1 downto 0);
|
s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
|
s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
|
s_dat_i: in std_logic_vector (width-1 downto 0);
|
s_dat_i: in std_logic_vector (width-1 downto 0);
|
s_dat_o: out std_logic_vector (width-1 downto 0);
|
s_dat_o: out std_logic_vector (width-1 downto 0);
|
s_cyc_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_ack_i: in std_logic;
|
s_ack_i: in std_logic;
|
s_err_i: in std_logic := '-';
|
s_err_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_we_o: out std_logic;
|
s_we_o: out std_logic;
|
s_stb_o: out std_logic;
|
s_stb_o: out std_logic;
|
|
|
-- interface to asyncron master device
|
-- interface to asyncron master device
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_rdn: in std_logic := '1';
|
a_rdn: in std_logic := '1';
|
a_wrn: in std_logic := '1';
|
a_wrn: in std_logic := '1';
|
a_cen: in std_logic := '1';
|
a_cen: in std_logic := '1';
|
a_byen: in std_logic_vector ((width/8)-1 downto 0);
|
a_byen: in std_logic_vector ((width/8)-1 downto 0);
|
a_waitn: out std_logic
|
a_waitn: out std_logic
|
);
|
);
|
end wb_async_master;
|
end wb_async_master;
|
|
|
architecture wb_async_master of wb_async_master is
|
architecture wb_async_master of wb_async_master is
|
component d_ff
|
component d_ff
|
port ( d : in STD_LOGIC;
|
port ( d : in STD_LOGIC;
|
clk: in STD_LOGIC;
|
clk: in STD_LOGIC;
|
ena: in STD_LOGIC := '1';
|
ena: in STD_LOGIC := '1';
|
clr: in STD_LOGIC := '0';
|
clr: in STD_LOGIC := '0';
|
pre: in STD_LOGIC := '0';
|
pre: in STD_LOGIC := '0';
|
q : out STD_LOGIC
|
q : out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
signal wg_clk, wg_pre, wg_q: std_logic;
|
signal wg_clk, wg_pre, wg_q: std_logic;
|
signal i_cyc_o, i_stb_o, i_we_o: std_logic;
|
signal i_cyc_o, i_stb_o, i_we_o: std_logic;
|
signal i_waitn: std_logic;
|
signal i_waitn: std_logic;
|
begin
|
begin
|
ctrl: process is
|
ctrl: process is
|
begin
|
begin
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
if (rst_i = '1') then
|
if (rst_i = '1') then
|
i_cyc_o <= '0';
|
i_cyc_o <= '0';
|
i_stb_o <= '0';
|
i_stb_o <= '0';
|
i_we_o <= '0';
|
i_we_o <= '0';
|
else
|
else
|
if (a_cen = '0') then
|
if (a_cen = '0') then
|
i_stb_o <= not (a_rdn and a_wrn);
|
i_stb_o <= not (a_rdn and a_wrn);
|
i_we_o <= not a_wrn;
|
i_we_o <= not a_wrn;
|
i_cyc_o <= '1';
|
i_cyc_o <= '1';
|
else
|
else
|
i_cyc_o <= '0';
|
i_cyc_o <= '0';
|
i_stb_o <= '0';
|
i_stb_o <= '0';
|
i_we_o <= '0';
|
i_we_o <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
s_cyc_o <= i_cyc_o and not i_waitn;
|
s_cyc_o <= i_cyc_o and not i_waitn;
|
s_stb_o <= i_stb_o and not i_waitn;
|
s_stb_o <= i_stb_o and not i_waitn;
|
s_we_o <= i_we_o and not i_waitn;
|
s_we_o <= i_we_o and not i_waitn;
|
|
|
w_ff1: d_ff port map (
|
w_ff1: d_ff port map (
|
d => s_ack_i,
|
d => s_ack_i,
|
clk => clk_i,
|
clk => clk_i,
|
ena => '1',
|
ena => '1',
|
clr => rst_i,
|
clr => rst_i,
|
pre => '0',
|
pre => '0',
|
q => wg_q
|
q => wg_q
|
);
|
);
|
|
|
wg_clk <= not a_cen;
|
wg_clk <= not a_cen;
|
wg_pre <= wg_q or rst_i;
|
wg_pre <= wg_q or rst_i;
|
w_ff2: d_ff port map (
|
w_ff2: d_ff port map (
|
d => '0',
|
d => '0',
|
clk => wg_clk,
|
clk => wg_clk,
|
ena => '1',
|
ena => '1',
|
clr => '0',
|
clr => '0',
|
pre => wg_pre,
|
pre => wg_pre,
|
q => i_waitn
|
q => i_waitn
|
);
|
);
|
a_waitn <= i_waitn;
|
a_waitn <= i_waitn;
|
|
|
s_adr_o <= a_addr;
|
s_adr_o <= a_addr;
|
negate: for i in s_sel_o'RANGE generate s_sel_o(i) <= not a_byen(i); end generate;
|
negate: for i in s_sel_o'RANGE generate s_sel_o(i) <= not a_byen(i); end generate;
|
s_dat_o <= a_data;
|
s_dat_o <= a_data;
|
|
|
a_data_out: process is
|
a_data_out: process is
|
begin
|
begin
|
wait on s_dat_i, a_rdn, a_cen;
|
wait on s_dat_i, a_rdn, a_cen;
|
if (a_rdn = '0' and a_cen = '0') then
|
if (a_rdn = '0' and a_cen = '0') then
|
a_data <= s_dat_i;
|
a_data <= s_dat_i;
|
else
|
else
|
a_data <= (others => 'Z');
|
a_data <= (others => 'Z');
|
end if;
|
end if;
|
end process;
|
end process;
|
end wb_async_master;
|
end wb_async_master;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- wb_async_slave
|
-- wb_async_slave
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
library work;
|
library work;
|
use work.technology.all;
|
use work.technology.all;
|
|
|
entity wb_async_slave is
|
entity wb_async_slave is
|
generic (
|
generic (
|
width: positive := 16;
|
width: positive := 16;
|
addr_width: positive := 20
|
addr_width: positive := 20
|
);
|
);
|
port (
|
port (
|
clk_i: in std_logic;
|
clk_i: in std_logic;
|
rst_i: in std_logic := '0';
|
rst_i: in std_logic := '0';
|
|
|
-- interface for wait-state generator state-machine
|
-- interface for wait-state generator state-machine
|
wait_state: in std_logic_vector (3 downto 0);
|
wait_state: in std_logic_vector (3 downto 0);
|
|
|
-- interface to wishbone master device
|
-- interface to wishbone master device
|
adr_i: in std_logic_vector (addr_width-1 downto 0);
|
adr_i: in std_logic_vector (addr_width-1 downto 0);
|
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
|
sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
|
dat_i: in std_logic_vector (width-1 downto 0);
|
dat_i: in std_logic_vector (width-1 downto 0);
|
dat_o: out std_logic_vector (width-1 downto 0);
|
dat_o: out std_logic_vector (width-1 downto 0);
|
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
|
dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
|
we_i: in std_logic;
|
we_i: in std_logic;
|
stb_i: in std_logic;
|
stb_i: in std_logic;
|
ack_o: out std_logic := '0';
|
ack_o: out std_logic := '0';
|
ack_oi: in std_logic := '-';
|
ack_oi: in std_logic := '-';
|
|
|
-- interface to async slave
|
-- interface to async slave
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
|
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
|
a_rdn: out std_logic := '1';
|
a_rdn: out std_logic := '1';
|
a_wrn: out std_logic := '1';
|
a_wrn: out std_logic := '1';
|
a_cen: out std_logic := '1';
|
a_cen: out std_logic := '1';
|
-- byte-enable signals
|
-- byte-enable signals
|
a_byen: out std_logic_vector ((width/8)-1 downto 0)
|
a_byen: out std_logic_vector ((width/8)-1 downto 0)
|
);
|
);
|
end wb_async_slave;
|
end wb_async_slave;
|
|
|
architecture wb_async_slave of wb_async_slave is
|
architecture wb_async_slave of wb_async_slave is
|
-- multiplexed access signals to memory
|
-- multiplexed access signals to memory
|
signal i_ack: std_logic;
|
signal i_ack: std_logic;
|
signal sm_ack: std_logic;
|
signal sm_ack: std_logic;
|
|
|
type states is (sm_idle, sm_wait, sm_deact);
|
type states is (sm_idle, sm_wait, sm_deact);
|
signal state: states;
|
signal state: states;
|
signal cnt: std_logic_vector(3 downto 0);
|
signal cnt: std_logic_vector(3 downto 0);
|
begin
|
begin
|
ack_o <= (stb_i and i_ack) or (not stb_i and ack_oi);
|
ack_o <= (stb_i and i_ack) or (not stb_i and ack_oi);
|
dat_o_gen: for i in dat_o'RANGE generate
|
dat_o_gen: for i in dat_o'RANGE generate
|
dat_o(i) <= (stb_i and a_data(i)) or (not stb_i and dat_oi(i));
|
dat_o(i) <= (stb_i and a_data(i)) or (not stb_i and dat_oi(i));
|
end generate;
|
end generate;
|
|
|
-- For 0WS operation i_ack is an async signal otherwise it's a sync one.
|
-- For 0WS operation i_ack is an async signal otherwise it's a sync one.
|
i_ack_gen: process is
|
i_ack_gen: process is
|
begin
|
begin
|
wait on sm_ack, stb_i, wait_state, state;
|
wait on sm_ack, stb_i, wait_state, state;
|
if (wait_state = "0000") then
|
if (wait_state = "0000") then
|
case (state) is
|
case (state) is
|
when sm_deact => i_ack <= '0';
|
when sm_deact => i_ack <= '0';
|
when others => i_ack <= stb_i;
|
when others => i_ack <= stb_i;
|
end case;
|
end case;
|
else
|
else
|
i_ack <= sm_ack;
|
i_ack <= sm_ack;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- SRAM signal-handler process
|
-- SRAM signal-handler process
|
sram_signals: process is
|
sram_signals: process is
|
begin
|
begin
|
wait on state,we_i,a_data,adr_i,rst_i, stb_i, sel_i, dat_i;
|
wait on state,we_i,a_data,adr_i,rst_i, stb_i, sel_i, dat_i;
|
if (rst_i = '1') then
|
if (rst_i = '1') then
|
a_wrn <= '1';
|
a_wrn <= '1';
|
a_rdn <= '1';
|
a_rdn <= '1';
|
a_cen <= '1';
|
a_cen <= '1';
|
a_addr <= (others => '-');
|
a_addr <= (others => '-');
|
a_data <= (others => 'Z');
|
a_data <= (others => 'Z');
|
a_byen <= (others => '1');
|
a_byen <= (others => '1');
|
else
|
else
|
case (state) is
|
case (state) is
|
when sm_deact =>
|
when sm_deact =>
|
a_wrn <= '1';
|
a_wrn <= '1';
|
a_rdn <= '1';
|
a_rdn <= '1';
|
a_cen <= '1';
|
a_cen <= '1';
|
a_addr <= (others => '-');
|
a_addr <= (others => '-');
|
a_data <= (others => 'Z');
|
a_data <= (others => 'Z');
|
a_byen <= (others => '1');
|
a_byen <= (others => '1');
|
when others =>
|
when others =>
|
a_addr <= adr_i;
|
a_addr <= adr_i;
|
a_rdn <= not (not we_i and stb_i);
|
a_rdn <= not (not we_i and stb_i);
|
a_wrn <= not (we_i and stb_i);
|
a_wrn <= not (we_i and stb_i);
|
a_cen <= not stb_i;
|
a_cen <= not stb_i;
|
a_byen <= not sel_i;
|
a_byen <= not sel_i;
|
if (we_i = '1') then
|
if (we_i = '1') then
|
a_data <= dat_i;
|
a_data <= dat_i;
|
else
|
else
|
a_data <= (others => 'Z');
|
a_data <= (others => 'Z');
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- Aysnc access state-machine.
|
-- Aysnc access state-machine.
|
async_sm: process is
|
async_sm: process is
|
-- variable cnt: std_logic_vector(3 downto 0) := "0000";
|
-- variable cnt: std_logic_vector(3 downto 0) := "0000";
|
-- variable state: states := init;
|
-- variable state: states := init;
|
begin
|
begin
|
wait until clk_i'EVENT and clk_i = '1';
|
wait until clk_i'EVENT and clk_i = '1';
|
if (rst_i = '1') then
|
if (rst_i = '1') then
|
state <= sm_idle;
|
state <= sm_idle;
|
cnt <= ((0) => '1', others => '0');
|
cnt <= ((0) => '1', others => '0');
|
sm_ack <= '0';
|
sm_ack <= '0';
|
else
|
else
|
case (state) is
|
case (state) is
|
when sm_idle =>
|
when sm_idle =>
|
-- Check if anyone needs access to the memory.
|
-- Check if anyone needs access to the memory.
|
-- it's rdy signal will already be pulled low, so we only have to start the access
|
-- it's rdy signal will already be pulled low, so we only have to start the access
|
if (stb_i = '1') then
|
if (stb_i = '1') then
|
case wait_state is
|
case wait_state is
|
when "0000" =>
|
when "0000" =>
|
sm_ack <= '1';
|
sm_ack <= '1';
|
state <= sm_deact;
|
state <= sm_deact;
|
when "0001" =>
|
when "0001" =>
|
sm_ack <= '1';
|
sm_ack <= '1';
|
cnt <= "0001";
|
cnt <= "0001";
|
state <= sm_wait;
|
state <= sm_wait;
|
when others =>
|
when others =>
|
sm_ack <= '0';
|
sm_ack <= '0';
|
cnt <= "0001";
|
cnt <= "0001";
|
state <= sm_wait;
|
state <= sm_wait;
|
end case;
|
end case;
|
end if;
|
end if;
|
when sm_wait =>
|
when sm_wait =>
|
if (cnt = wait_state) then
|
if (cnt = wait_state) then
|
-- wait cycle completed.
|
-- wait cycle completed.
|
state <= sm_deact;
|
state <= sm_deact;
|
sm_ack <= '0';
|
sm_ack <= '0';
|
cnt <= "0000";
|
cnt <= "0000";
|
else
|
else
|
if (add_one(cnt) = wait_state) then
|
if (add_one(cnt) = wait_state) then
|
sm_ack <= '1';
|
sm_ack <= '1';
|
else
|
else
|
sm_ack <= '0';
|
sm_ack <= '0';
|
end if;
|
end if;
|
cnt <= add_one(cnt);
|
cnt <= add_one(cnt);
|
end if;
|
end if;
|
when sm_deact =>
|
when sm_deact =>
|
if (stb_i = '1') then
|
if (stb_i = '1') then
|
case wait_state is
|
case wait_state is
|
when "0000" =>
|
when "0000" =>
|
cnt <= "0000";
|
cnt <= "0000";
|
sm_ack <= '0';
|
sm_ack <= '0';
|
state <= sm_wait;
|
state <= sm_wait;
|
when others =>
|
when others =>
|
sm_ack <= '0';
|
sm_ack <= '0';
|
cnt <= "0000";
|
cnt <= "0000";
|
state <= sm_wait;
|
state <= sm_wait;
|
end case;
|
end case;
|
else
|
else
|
sm_ack <= '0';
|
sm_ack <= '0';
|
state <= sm_idle;
|
state <= sm_idle;
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
end wb_async_slave;
|
end wb_async_slave;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- wb_arbiter
|
-- wb_arbiter
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
library work;
|
library work;
|
use work.technology.all;
|
use work.technology.all;
|
|
|
entity wb_arbiter is
|
entity wb_arbiter is
|
port (
|
port (
|
-- clk: in std_logic;
|
-- clk: in std_logic;
|
rst_i: in std_logic := '0';
|
rst_i: in std_logic := '0';
|
|
|
-- interface to master device a
|
-- interface to master device a
|
a_we_i: in std_logic;
|
a_we_i: in std_logic;
|
a_stb_i: in std_logic;
|
a_stb_i: in std_logic;
|
a_cyc_i: in std_logic;
|
a_cyc_i: in std_logic;
|
a_ack_o: out std_logic;
|
a_ack_o: out std_logic;
|
a_ack_oi: in std_logic := '-';
|
a_ack_oi: in std_logic := '-';
|
a_err_o: out std_logic;
|
a_err_o: out std_logic;
|
a_err_oi: in std_logic := '-';
|
a_err_oi: in std_logic := '-';
|
a_rty_o: out std_logic;
|
a_rty_o: out std_logic;
|
a_rty_oi: in std_logic := '-';
|
a_rty_oi: in std_logic := '-';
|
|
|
-- interface to master device b
|
-- interface to master device b
|
b_we_i: in std_logic;
|
b_we_i: in std_logic;
|
b_stb_i: in std_logic;
|
b_stb_i: in std_logic;
|
b_cyc_i: in std_logic;
|
b_cyc_i: in std_logic;
|
b_ack_o: out std_logic;
|
b_ack_o: out std_logic;
|
b_ack_oi: in std_logic := '-';
|
b_ack_oi: in std_logic := '-';
|
b_err_o: out std_logic;
|
b_err_o: out std_logic;
|
b_err_oi: in std_logic := '-';
|
b_err_oi: in std_logic := '-';
|
b_rty_o: out std_logic;
|
b_rty_o: out std_logic;
|
b_rty_oi: in std_logic := '-';
|
b_rty_oi: in std_logic := '-';
|
|
|
-- interface to shared devices
|
-- interface to shared devices
|
s_we_o: out std_logic;
|
s_we_o: out std_logic;
|
s_stb_o: out std_logic;
|
s_stb_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_cyc_o: out std_logic;
|
s_ack_i: in std_logic;
|
s_ack_i: in std_logic;
|
s_err_i: in std_logic := '-';
|
s_err_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
s_rty_i: in std_logic := '-';
|
|
|
mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
|
mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
|
|
|
-- misc control lines
|
-- misc control lines
|
priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
|
priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
|
);
|
);
|
end wb_arbiter;
|
end wb_arbiter;
|
|
|
-- This acthitecture is a clean asyncron state-machine. However it cannot be mapped to FPGA architecture
|
-- This acthitecture is a clean asyncron state-machine. However it cannot be mapped to FPGA architecture
|
architecture behaviour of wb_arbiter is
|
architecture behaviour of wb_arbiter is
|
type states is (idle,aa,ba);
|
type states is (idle,aa,ba);
|
signal i_mux_signal: std_logic;
|
signal i_mux_signal: std_logic;
|
|
|
signal e_state: states;
|
signal e_state: states;
|
begin
|
begin
|
mux_signal <= i_mux_signal;
|
mux_signal <= i_mux_signal;
|
|
|
sm: process is
|
sm: process is
|
variable state: states;
|
variable state: states;
|
begin
|
begin
|
wait on a_cyc_i, b_cyc_i, priority, rst_i;
|
wait on a_cyc_i, b_cyc_i, priority, rst_i;
|
if (rst_i = '1') then
|
if (rst_i = '1') then
|
state := idle;
|
state := idle;
|
i_mux_signal <= priority;
|
i_mux_signal <= priority;
|
else
|
else
|
case (state) is
|
case (state) is
|
when idle =>
|
when idle =>
|
if (a_cyc_i = '1' and (priority = '0' or b_cyc_i = '0')) then
|
if (a_cyc_i = '1' and (priority = '0' or b_cyc_i = '0')) then
|
state := aa;
|
state := aa;
|
i_mux_signal <= '0';
|
i_mux_signal <= '0';
|
elsif (b_cyc_i = '1' and (priority = '1' or a_cyc_i = '0')) then
|
elsif (b_cyc_i = '1' and (priority = '1' or a_cyc_i = '0')) then
|
state := ba;
|
state := ba;
|
i_mux_signal <= '1';
|
i_mux_signal <= '1';
|
else
|
else
|
i_mux_signal <= priority;
|
i_mux_signal <= priority;
|
end if;
|
end if;
|
when aa =>
|
when aa =>
|
if (a_cyc_i = '0') then
|
if (a_cyc_i = '0') then
|
if (b_cyc_i = '1') then
|
if (b_cyc_i = '1') then
|
state := ba;
|
state := ba;
|
i_mux_signal <= '1';
|
i_mux_signal <= '1';
|
else
|
else
|
state := idle;
|
state := idle;
|
i_mux_signal <= priority;
|
i_mux_signal <= priority;
|
end if;
|
end if;
|
else
|
else
|
i_mux_signal <= '0';
|
i_mux_signal <= '0';
|
end if;
|
end if;
|
when ba =>
|
when ba =>
|
if (b_cyc_i = '0') then
|
if (b_cyc_i = '0') then
|
if (a_cyc_i = '1') then
|
if (a_cyc_i = '1') then
|
state := aa;
|
state := aa;
|
i_mux_signal <= '0';
|
i_mux_signal <= '0';
|
else
|
else
|
state := idle;
|
state := idle;
|
i_mux_signal <= priority;
|
i_mux_signal <= priority;
|
end if;
|
end if;
|
else
|
else
|
i_mux_signal <= '1';
|
i_mux_signal <= '1';
|
end if;
|
end if;
|
end case;
|
end case;
|
end if;
|
end if;
|
e_state <= state;
|
e_state <= state;
|
end process;
|
end process;
|
|
|
signal_mux: process is
|
signal_mux: process is
|
begin
|
begin
|
wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
|
wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
|
b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
|
b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
|
s_ack_i, s_err_i, s_rty_i, i_mux_signal;
|
s_ack_i, s_err_i, s_rty_i, i_mux_signal;
|
if (i_mux_signal = '0') then
|
if (i_mux_signal = '0') then
|
s_we_o <= a_we_i;
|
s_we_o <= a_we_i;
|
s_stb_o <= a_stb_i;
|
s_stb_o <= a_stb_i;
|
s_cyc_o <= a_cyc_i;
|
s_cyc_o <= a_cyc_i;
|
a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
|
a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
|
a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
|
a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
|
a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
|
a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
|
b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
|
b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
|
b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
|
b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
|
b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
|
b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
|
else
|
else
|
s_we_o <= b_we_i;
|
s_we_o <= b_we_i;
|
s_stb_o <= b_stb_i;
|
s_stb_o <= b_stb_i;
|
s_cyc_o <= b_cyc_i;
|
s_cyc_o <= b_cyc_i;
|
b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
|
b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
|
b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
|
b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
|
b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
|
b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
|
a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
|
a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
|
a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
|
a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
|
a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
|
a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
|
end if;
|
end if;
|
end process;
|
end process;
|
end behaviour;
|
end behaviour;
|
|
|
-- This acthitecture is a more-or-less structural implementation. Fits for FPGA realization.
|
-- This acthitecture is a more-or-less structural implementation. Fits for FPGA realization.
|
architecture FPGA of wb_arbiter is
|
architecture FPGA of wb_arbiter is
|
component d_ff
|
component d_ff
|
port ( d : in STD_LOGIC;
|
port ( d : in STD_LOGIC;
|
clk: in STD_LOGIC;
|
clk: in STD_LOGIC;
|
ena: in STD_LOGIC := '1';
|
ena: in STD_LOGIC := '1';
|
clr: in STD_LOGIC := '0';
|
clr: in STD_LOGIC := '0';
|
pre: in STD_LOGIC := '0';
|
pre: in STD_LOGIC := '0';
|
q : out STD_LOGIC
|
q : out STD_LOGIC
|
);
|
);
|
end component;
|
end component;
|
|
|
signal i_mux_signal: std_logic;
|
signal i_mux_signal: std_logic;
|
|
|
type states is (idle,aa,ba,XX);
|
type states is (idle,aa,ba,XX);
|
signal e_state: states;
|
signal e_state: states;
|
|
|
-- signals for a DFF in FPGA
|
-- signals for a DFF in FPGA
|
signal idle_s, aa_s, ba_s: std_logic;
|
signal idle_s, aa_s, ba_s: std_logic;
|
|
|
signal aa_clk, aa_ena, aa_clr, aa_pre: std_logic;
|
signal aa_clk, aa_ena, aa_clr, aa_pre: std_logic;
|
signal ba_clk, ba_ena, ba_clr, ba_pre: std_logic;
|
signal ba_clk, ba_ena, ba_clr, ba_pre: std_logic;
|
|
|
begin
|
begin
|
mux_signal <= i_mux_signal;
|
mux_signal <= i_mux_signal;
|
|
|
idle_s <= not (a_cyc_i or b_cyc_i);
|
idle_s <= not (a_cyc_i or b_cyc_i);
|
|
|
aa_clr <= rst_i or not a_cyc_i;
|
aa_clr <= rst_i or not a_cyc_i;
|
aa_clk <= a_cyc_i;
|
aa_clk <= a_cyc_i;
|
aa_ena <= not b_cyc_i and priority;
|
aa_ena <= not b_cyc_i and priority;
|
aa_pre <= (a_cyc_i and not priority and not ba_s) or (a_cyc_i and not b_cyc_i);
|
aa_pre <= (a_cyc_i and not priority and not ba_s) or (a_cyc_i and not b_cyc_i);
|
aa_ff: d_ff port map (
|
aa_ff: d_ff port map (
|
d => '1',
|
d => '1',
|
clk => aa_clk,
|
clk => aa_clk,
|
ena => aa_ena,
|
ena => aa_ena,
|
clr => aa_clr,
|
clr => aa_clr,
|
pre => aa_pre,
|
pre => aa_pre,
|
q => aa_s
|
q => aa_s
|
);
|
);
|
|
|
ba_clr <= rst_i or not b_cyc_i;
|
ba_clr <= rst_i or not b_cyc_i;
|
ba_clk <= b_cyc_i;
|
ba_clk <= b_cyc_i;
|
ba_ena <= not a_cyc_i and not priority;
|
ba_ena <= not a_cyc_i and not priority;
|
ba_pre <= (b_cyc_i and priority and not aa_s) or (b_cyc_i and not a_cyc_i);
|
ba_pre <= (b_cyc_i and priority and not aa_s) or (b_cyc_i and not a_cyc_i);
|
ba_ff: d_ff port map (
|
ba_ff: d_ff port map (
|
d => '1',
|
d => '1',
|
clk => ba_clk,
|
clk => ba_clk,
|
ena => ba_ena,
|
ena => ba_ena,
|
clr => ba_clr,
|
clr => ba_clr,
|
pre => ba_pre,
|
pre => ba_pre,
|
q => ba_s
|
q => ba_s
|
);
|
);
|
|
|
i_mux_signal <= (priority and idle_s) or ba_s;
|
i_mux_signal <= (priority and idle_s) or ba_s;
|
|
|
signal_mux: process is
|
signal_mux: process is
|
begin
|
begin
|
wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
|
wait on a_we_i, a_stb_i, a_ack_oi, a_err_oi, a_rty_oi, a_cyc_i,
|
b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
|
b_we_i, b_stb_i, b_ack_oi, b_err_oi, b_rty_oi, b_cyc_i,
|
s_ack_i, s_err_i, s_rty_i, i_mux_signal;
|
s_ack_i, s_err_i, s_rty_i, i_mux_signal;
|
if (i_mux_signal = '0') then
|
if (i_mux_signal = '0') then
|
s_we_o <= a_we_i;
|
s_we_o <= a_we_i;
|
s_stb_o <= a_stb_i;
|
s_stb_o <= a_stb_i;
|
s_cyc_o <= a_cyc_i;
|
s_cyc_o <= a_cyc_i;
|
a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
|
a_ack_o <= (a_stb_i and s_ack_i) or (not a_stb_i and a_ack_oi);
|
a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
|
a_err_o <= (a_stb_i and s_err_i) or (not a_stb_i and a_err_oi);
|
a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
|
a_rty_o <= (a_stb_i and s_rty_i) or (not a_stb_i and a_rty_oi);
|
b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
|
b_ack_o <= (b_stb_i and '0') or (not b_stb_i and b_ack_oi);
|
b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
|
b_err_o <= (b_stb_i and '0') or (not b_stb_i and b_err_oi);
|
b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
|
b_rty_o <= (b_stb_i and '0') or (not b_stb_i and b_rty_oi);
|
else
|
else
|
s_we_o <= b_we_i;
|
s_we_o <= b_we_i;
|
s_stb_o <= b_stb_i;
|
s_stb_o <= b_stb_i;
|
s_cyc_o <= b_cyc_i;
|
s_cyc_o <= b_cyc_i;
|
b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
|
b_ack_o <= (b_stb_i and s_ack_i) or (not b_stb_i and b_ack_oi);
|
b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
|
b_err_o <= (b_stb_i and s_err_i) or (not b_stb_i and b_err_oi);
|
b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
|
b_rty_o <= (b_stb_i and s_rty_i) or (not b_stb_i and b_rty_oi);
|
a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
|
a_ack_o <= (a_stb_i and '0') or (not a_stb_i and a_ack_oi);
|
a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
|
a_err_o <= (a_stb_i and '0') or (not a_stb_i and a_err_oi);
|
a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
|
a_rty_o <= (a_stb_i and '0') or (not a_stb_i and a_rty_oi);
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
gen_e_state: process is
|
gen_e_state: process is
|
begin
|
begin
|
wait on idle_s,aa_s,ba_s;
|
wait on idle_s,aa_s,ba_s;
|
if (idle_s = '1' and ba_s = '0' and aa_s = '0') then e_state <= idle;
|
if (idle_s = '1' and ba_s = '0' and aa_s = '0') then e_state <= idle;
|
elsif (idle_s = '0' and ba_s = '1' and aa_s = '0') then e_state <= aa;
|
elsif (idle_s = '0' and ba_s = '1' and aa_s = '0') then e_state <= aa;
|
elsif (idle_s = '0' and ba_s = '0' and aa_s = '1') then e_state <= ba;
|
elsif (idle_s = '0' and ba_s = '0' and aa_s = '1') then e_state <= ba;
|
else e_state <= XX;
|
else e_state <= XX;
|
end if;
|
end if;
|
end process;
|
end process;
|
end FPGA;
|
end FPGA;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- wb_out_reg
|
-- wb_out_reg
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
|
|
library work;
|
library work;
|
use work.technology.all;
|
use work.technology.all;
|
|
|
entity wb_out_reg is
|
entity wb_out_reg is
|
generic (
|
generic (
|
width : positive := 8;
|
width : positive := 8;
|
bus_width: positive := 8;
|
bus_width: positive := 8;
|
offset: integer := 0
|
offset: integer := 0
|
);
|
);
|
port (
|
port (
|
clk_i: in std_logic;
|
clk_i: in std_logic;
|
rst_i: in std_logic;
|
rst_i: in std_logic;
|
rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
|
rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
|
|
|
dat_i: in std_logic_vector (bus_width-1 downto 0);
|
dat_i: in std_logic_vector (bus_width-1 downto 0);
|
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
|
dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
|
dat_o: out std_logic_vector (bus_width-1 downto 0);
|
dat_o: out std_logic_vector (bus_width-1 downto 0);
|
q: out std_logic_vector (width-1 downto 0);
|
q: out std_logic_vector (width-1 downto 0);
|
we_i: in std_logic;
|
we_i: in std_logic;
|
stb_i: in std_logic;
|
stb_i: in std_logic;
|
ack_o: out std_logic;
|
ack_o: out std_logic;
|
ack_oi: in std_logic := '-'
|
ack_oi: in std_logic := '-'
|
);
|
);
|
end wb_out_reg;
|
end wb_out_reg;
|
|
|
architecture wb_out_reg of wb_out_reg is
|
architecture wb_out_reg of wb_out_reg is
|
signal content : std_logic_vector (width-1 downto 0);
|
signal content : std_logic_vector (width-1 downto 0);
|
begin
|
begin
|
-- output bus handling with logic
|
-- output bus handling with logic
|
gen_dat_o: process is
|
gen_dat_o: process is
|
variable rd_sel: std_logic;
|
variable rd_sel: std_logic;
|
begin
|
begin
|
wait on dat_oi, we_i, stb_i, content;
|
wait on dat_oi, we_i, stb_i, content;
|
rd_sel := stb_i and not we_i;
|
rd_sel := stb_i and not we_i;
|
for i in bus_width-1 downto 0 loop
|
for i in bus_width-1 downto 0 loop
|
if (i >= offset and i < offset+width) then
|
if (i >= offset and i < offset+width) then
|
dat_o(i) <= (dat_oi(i) and not rd_sel) or (content(i-offset) and rd_sel);
|
dat_o(i) <= (dat_oi(i) and not rd_sel) or (content(i-offset) and rd_sel);
|
else
|
else
|
dat_o(i) <= dat_oi(i);
|
dat_o(i) <= dat_oi(i);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
end process;
|
end process;
|
|
|
-- this item never generates any wait-states
|
-- this item never generates any wait-states
|
ack_o <= stb_i or ack_oi;
|
ack_o <= stb_i or ack_oi;
|
|
|
reg: process is
|
reg: process is
|
begin
|
begin
|
wait until clk_i'EVENT and clk_i='1';
|
wait until clk_i'EVENT and clk_i='1';
|
if (rst_i = '1') then
|
if (rst_i = '1') then
|
content <= rst_val;
|
content <= rst_val;
|
else
|
else
|
if (stb_i = '1' and we_i = '1') then
|
if (stb_i = '1' and we_i = '1') then
|
content <= dat_i(width+offset-1 downto offset);
|
content <= dat_i(width+offset-1 downto offset);
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
q <= content;
|
q <= content;
|
end wb_out_reg;
|
end wb_out_reg;
|
|
|
