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--
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-- Horizontal and vertical sync generator.
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--
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-- (c) Copyright Andras Tantos <tantos@opencores.org> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity hv_sync is
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port (
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clk: in std_logic;
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pix_clk_en: in std_logic := '1';
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reset: in std_logic := '0';
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hbs: in std_logic_vector(7 downto 0);
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hss: in std_logic_vector(7 downto 0);
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hse: in std_logic_vector(7 downto 0);
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htotal: in std_logic_vector(7 downto 0);
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vbs: in std_logic_vector(7 downto 0);
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vss: in std_logic_vector(7 downto 0);
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vse: in std_logic_vector(7 downto 0);
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vtotal: in std_logic_vector(7 downto 0);
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic
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);
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end hv_sync;
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architecture hv_sync of hv_sync is
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component sync_gen
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port (
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clk: in std_logic;
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clk_en: in std_logic;
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reset: in std_logic := '0';
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bs: in std_logic_vector(7 downto 0);
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ss: in std_logic_vector(7 downto 0);
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se: in std_logic_vector(7 downto 0);
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total: in std_logic_vector(7 downto 0);
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sync: out std_logic;
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blank: out std_logic;
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tc: out std_logic;
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count: out std_logic_vector (7 downto 0)
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);
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end component;
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signal h_blank_i: std_logic;
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signal v_blank_i: std_logic;
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signal h_tc_i: std_logic;
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signal hcen: std_logic;
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signal vcen: std_logic;
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constant h_pre_div_factor: integer := 3;
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constant v_pre_div_factor: integer := 3;
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subtype h_div_var is integer range 0 to h_pre_div_factor;
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subtype v_div_var is integer range 0 to v_pre_div_factor;
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begin
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h_pre_div : process is
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variable cntr: h_div_var;
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begin
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wait until clk'EVENT and clk='1';
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if (reset = '1') then
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cntr := 0;
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hcen <= '0';
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else
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if (pix_clk_en='1') then
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if (cntr = h_pre_div_factor) then
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cntr := 0;
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hcen <= '1';
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else
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cntr := cntr+1;
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hcen <= '0';
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end if;
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else
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hcen <= '0';
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end if;
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end if;
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end process;
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h_sync_gen : sync_gen
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port map (
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clk => clk,
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clk_en => hcen,
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reset => reset,
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bs => hbs,
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ss => hss,
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se => hse,
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total => htotal,
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sync => h_sync,
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blank => h_blank_i,
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tc => h_tc_i
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);
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h_tc <= h_tc_i;
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v_pre_div : process is
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variable cntr: v_div_var;
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begin
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wait until clk'EVENT and clk='1';
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if (reset = '1') then
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cntr := 0;
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vcen <= '0';
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else
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if (h_tc_i='1') then
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if (cntr = v_pre_div_factor) then
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cntr := 0;
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vcen <= '1';
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else
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cntr := cntr+1;
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vcen <= '0';
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end if;
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else
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vcen <= '0';
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end if;
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end if;
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end process;
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v_sync_gen : sync_gen
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port map (
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clk => clk,
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clk_en => vcen,
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reset => reset,
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bs => vbs,
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ss => vss,
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se => vse,
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total => vtotal,
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sync => v_sync,
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blank => v_blank_i,
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tc => v_tc
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);
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blank <= h_blank_i or v_blank_i;
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h_blank <= h_blank_i;
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v_blank <= v_blank_i;
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end hv_sync;
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