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--
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-- File: mem_reader.vhd
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity mem_reader is
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generic (
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v_mem_width: positive := 16;
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v_addr_width: positive:= 20;
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fifo_size: positive := 256;
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dual_scan_fifo_size: positive := 256
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);
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port (
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clk: in std_logic;
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clk_en: in std_logic;
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pix_clk_en: in std_logic;
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reset: in std_logic := '0';
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v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
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v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
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fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
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bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
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multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
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-- Can be githces on it!!! Don't clock by it!!!
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high_prior: out std_logic; -- signals to the memory arbitrer to give high
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-- priority to the video engine
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v_mem_rd: out std_logic; -- video memory read request
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v_mem_rdy: in std_logic; -- video memory data ready
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v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
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v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
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blank: in std_logic; -- video sync generator blank output
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h_tc: in std_logic; -- horizontal sync pulse. Must be 1 clock wide!
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end mem_reader;
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architecture mem_reader of mem_reader is
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component fifo
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generic (fifo_width : positive;
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used_width : positive;
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fifo_depth : positive
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);
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port (d_in : in std_logic_vector(fifo_width-1 downto 0);
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clk : in std_logic;
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wr : in std_logic;
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rd : in std_logic;
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a_clr : in std_logic := '0';
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s_clr : in std_logic := '0';
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d_out : out std_logic_vector(fifo_width-1 downto 0);
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used : out std_logic_vector(used_width-1 downto 0);
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full : out std_logic;
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empty : out std_logic
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);
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end component;
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signal fifo_rd: std_logic;
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signal fifo_out: std_logic_vector(v_mem_width-1 downto 0);
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signal video_fifo_out: std_logic_vector(v_mem_width-1 downto 0);
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signal video_fifo_usedw: std_logic_vector(7 downto 0);
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signal video_fifo_rd: std_logic;
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signal video_fifo_full: std_logic;
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signal video_fifo_empty: std_logic;
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signal ds_fifo_out: std_logic_vector(v_mem_width-1 downto 0);
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-- signal ds_fifo_usedw: std_logic_vector(7 downto 0);
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signal ds_fifo_rd: std_logic;
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signal ds_fifo_clr: std_logic;
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-- signal ds_fifo_full: std_logic;
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-- signal ds_fifo_empty: std_logic;
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signal i_video_out: std_logic_vector(7 downto 0);
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signal ds_mode: std_logic;
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subtype pixel_cntr_var is integer range 0 to 7;
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-- signal i_v_mem_rd: std_logic := '0';
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begin
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-- memory decoupler FIFO
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pixel_fifo: fifo
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generic map (
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fifo_width => v_mem_width,
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used_width => 8,
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fifo_depth => fifo_size
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)
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port map (
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d_in => v_mem_data,
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clk => clk,
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wr => v_mem_rdy,
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rd => video_fifo_rd,
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-- a_clr => '0',
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a_clr => reset,
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s_clr => reset,
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full => video_fifo_full,
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d_out => video_fifo_out,
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used => video_fifo_usedw,
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empty => video_fifo_empty
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);
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-- dual-scan FIFO
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ds_pixel_fifo: fifo
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generic map (
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fifo_width => v_mem_width,
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used_width => 8,
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fifo_depth => dual_scan_fifo_size
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)
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port map (
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d_in => fifo_out,
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clk => clk,
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wr => fifo_rd,
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rd => ds_fifo_rd,
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-- a_clr => '0',
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a_clr => reset,
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s_clr => ds_fifo_clr,
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d_out => ds_fifo_out
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);
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-- Multiplexer for DS data handling
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fifo_mux: for i in v_mem_width-1 downto 0 generate
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begin
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fifo_out(i) <= (video_fifo_out(i) and not ds_mode) or (ds_fifo_out(i) and ds_mode);
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-- fifo_out(i) <= (video_fifo_out(i) and not ds_mode);
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end generate;
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--fifo_out <= (video_fifo_out and not ds_mode);
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ds_fifo_rd <= ('0' and not ds_mode) or (fifo_rd and ds_mode);
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video_fifo_rd <= (fifo_rd and not ds_mode) or ('0' and ds_mode);
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-- Counter handles DS
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ds_counter : process is
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variable cnt: std_logic_vector(1 downto 0);
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begin
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wait until clk'EVENT and clk = '1';
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if (reset = '1') then
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cnt := (others => '0');
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ds_fifo_clr <= '1';
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ds_mode <= '0';
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else
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if (clk_en = '1') then
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if (h_tc = '1') then
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if (is_zero(cnt)) then
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ds_mode <= '0';
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ds_fifo_clr <= '1';
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else
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ds_mode <= '1';
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ds_fifo_clr <= '0';
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end if;
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if (cnt = multi_scan) then
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cnt := (others => '0');
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else
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cnt := add_one(cnt);
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end if;
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else
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ds_fifo_clr <= '0';
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end if;
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else
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ds_fifo_clr <= '1';
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ds_mode <= '0';
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end if;
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end if;
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end process;
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-- Pixel data reader state machine
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pixel_cntr : process is
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variable pixel_cnt: std_logic_vector(v_addr_width-1 downto 0);
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begin
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wait until clk'EVENT and clk='1';
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if (reset = '1') then
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pixel_cnt := v_mem_start;
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else
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-- A little cheet. It won't work with constant v_mem_rdy.
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if (v_mem_rdy = '1') then
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-- data is already written to the FIFO, all we need to do is to update the counter,
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-- and remove the request
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if (pixel_cnt = v_mem_end) then
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pixel_cnt := v_mem_start;
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else
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pixel_cnt := add_one(pixel_cnt);
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end if;
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end if;
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end if;
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v_mem_addr <= pixel_cnt;
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end process;
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v_mem_rd <= (not video_fifo_full) and (not reset);
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-- Pixel data output state machine.
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pixel_output: process is
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subtype pixel_cntr_var is integer range 0 to v_mem_width-1;
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variable pixel_cntr : pixel_cntr_var;
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variable shift_reg : std_logic_vector (v_mem_width-1 downto 0);
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type rst_states is (in_reset,read,normal);
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variable rst_state : rst_states := in_reset;
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begin
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wait until clk'EVENT and clk='1';
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if (reset = '1') then
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fifo_rd <= '0';
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i_video_out <= (others => '0');
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shift_reg := (others => '0');
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pixel_cntr := 0;
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rst_state := in_reset;
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else
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if (not (rst_state = normal)) then
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-- perform one read after reset otherwise the picture will be shifted rigth one pixel
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case (rst_state) is
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when in_reset =>
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if (video_fifo_empty = '0') then
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fifo_rd <= '1';
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rst_state := read;
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else
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fifo_rd <= '0';
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end if;
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when read =>
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pixel_cntr := 0;
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shift_reg := fifo_out;
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fifo_rd <= '0';
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rst_state := normal;
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when others =>
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end case;
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else
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if (pix_clk_en = '0') then
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fifo_rd <= '0'; -- clear any pending read requests
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else
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if (blank = '1') then
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fifo_rd <= '0'; -- clear any pending read requests
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i_video_out <= (others => '0'); -- disable output
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-- i_video_out <= (others => 'U'); -- disable output
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else
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case (bpp) is
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when "00" =>
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-- shift next data to the output and optionally read the next data from the fifo
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i_video_out(0) <= shift_reg(v_mem_width-1);
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i_video_out(7 downto 1) <= (others => '0');
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if (pixel_cntr = v_mem_width-1) then
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-- Read next data
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pixel_cntr := 0;
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shift_reg := fifo_out;
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fifo_rd <= '0';
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elsif (pixel_cntr = v_mem_width-2) then
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-- Request next data from FIFO
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '1';
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shift_reg := sl(shift_reg,1);
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else
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-- Simple increment
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '0';
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shift_reg := sl(shift_reg,1);
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end if;
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when "01" =>
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-- shift next data to the output and optionally read the next data from the fifo
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i_video_out(1 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-2);
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i_video_out(7 downto 2) <= (others => '0');
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if (pixel_cntr = v_mem_width/2-1) then
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-- Read next data
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pixel_cntr := 0;
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shift_reg := fifo_out;
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fifo_rd <= '0';
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elsif (pixel_cntr = v_mem_width/2-2) then
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-- Request next data from FIFO
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '1';
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shift_reg := sl(shift_reg,2);
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else
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-- Simple increment
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '0';
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shift_reg := sl(shift_reg,2);
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end if;
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when "10" =>
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-- shift next data to the output and optionally read the next data from the fifo
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i_video_out(3 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-4);
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i_video_out(7 downto 4) <= (others => '0');
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if (pixel_cntr = v_mem_width/4-1) then
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-- Read next data
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pixel_cntr := 0;
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shift_reg := fifo_out;
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fifo_rd <= '0';
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elsif (pixel_cntr = v_mem_width/4-2) then
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-- Request next data from FIFO
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '1';
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shift_reg := sl(shift_reg,4);
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else
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-- Simple increment
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '0';
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shift_reg := sl(shift_reg,4);
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end if;
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when "11" =>
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if (v_mem_width = 8) then
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-- 8 bit memory with 8 bit output: every clock reads a byte from the fifo.
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fifo_rd <= '1';
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i_video_out(7 downto 0) <= fifo_out;
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else
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-- shift next data to the output and optionally read the next data from the fifo
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i_video_out(7 downto 0) <= shift_reg(v_mem_width-1 downto v_mem_width-8);
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if (pixel_cntr = v_mem_width/8-1) then
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-- Read next data
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pixel_cntr := 0;
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shift_reg := fifo_out;
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fifo_rd <= '0';
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elsif (pixel_cntr = v_mem_width/8-2) then
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-- Request next data from FIFO
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '1';
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shift_reg := sl(shift_reg,8);
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else
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-- Simple increment
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pixel_cntr := pixel_cntr + 1;
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fifo_rd <= '0';
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shift_reg := sl(shift_reg,8);
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end if;
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end if;
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when others => -- Unsupported setting. Do nothing
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i_video_out(7 downto 0) <= (others => '0');
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fifo_rd <= '0';
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pixel_cntr := 0;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process;
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video_out <= i_video_out;
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-- Simple logic generates the high_prior output
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priority: process is
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begin
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wait on video_fifo_usedw,fifo_treshold,video_fifo_full;
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if (video_fifo_usedw < fifo_treshold and video_fifo_full = '0') then
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high_prior <= '1';
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else
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high_prior <= '0';
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end if;
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end process;
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end mem_reader;
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