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--
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-- Palette RAM.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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-------------------------------------------------------------------------------
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--
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-- wb_pal_ram
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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use wb_tk.all;
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entity wb_pal_ram is
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generic (
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cpu_dat_width: positive := 8;
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cpu_adr_width: positive := 9;
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v_dat_width: positive := 16;
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v_adr_width: positive := 8
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);
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port (
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-- Wishbone interface to CPU (write-only support)
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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-- sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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err_o: out std_logic;
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err_oi: in std_logic := '-';
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-- rty_o: out std_logic;
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-- rty_oi: in std_logic := '-';
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we_i: in std_logic;
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stb_i: in std_logic;
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-- Interface to the video output
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blank: in std_logic;
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v_dat_i: in std_logic_vector(v_adr_width-1 downto 0);
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v_dat_o: out std_logic_vector(v_dat_width-1 downto 0)
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);
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end wb_pal_ram;
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architecture wb_pal_ram of wb_pal_ram is
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component dpram
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generic (
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data_width : positive;
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addr_width : positive
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);
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port (
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clk : in std_logic;
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r_d_out : out std_logic_vector(data_width-1 downto 0);
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r_rd : in std_logic;
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r_clk_en : in std_logic;
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r_addr : in std_logic_vector(addr_width-1 downto 0);
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w_d_in : in std_logic_vector(data_width-1 downto 0);
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w_wr : in std_logic;
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w_clk_en : in std_logic;
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w_addr : in std_logic_vector(addr_width-1 downto 0)
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);
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end component;
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component wb_out_reg
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generic (
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width : positive := 8;
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bus_width: positive := 8;
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offset: integer := 0
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
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cyc_i: in std_logic := '1';
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stb_i: in std_logic;
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sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
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we_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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q: out std_logic_vector (width-1 downto 0)
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);
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end component;
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signal mem_we: std_logic;
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signal mem_rd: std_logic;
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signal mem_d_in: std_logic_vector(v_dat_width-1 downto 0);
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signal ext_reg_stb: std_logic;
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signal mem_stb: std_logic;
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signal mem_d_out: std_logic_vector(v_dat_width-1 downto 0);
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begin
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mem_stb_gen1: if (cpu_dat_width < v_dat_width) generate
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mem_stb <= '1' WHEN adr_i(cpu_adr_width-v_adr_width-1 downto 0)=(cpu_adr_width-v_adr_width-1 downto 0 =>'1') ELSE '0';
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end generate;
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mem_stb_gen2: if (cpu_dat_width >= v_dat_width) generate
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mem_stb <= '1';
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end generate;
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mem_we <= we_i and stb_i and cyc_i and mem_stb;
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mem_rd <= not blank;
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mem_d_in_gen1: if (cpu_dat_width < v_dat_width) generate
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mem_d_in(v_dat_width-1 downto v_dat_width-cpu_dat_width) <= dat_i;
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end generate;
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mem_d_in_gen2: if (cpu_dat_width >= v_dat_width) generate
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mem_d_in(v_dat_width-1 downto 0) <= dat_i(mem_d_in'RANGE);
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end generate;
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tech_ram: dpram
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generic map(
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data_width => v_dat_width,
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addr_width => v_adr_width
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)
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port map (
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clk => clk_i,
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r_d_out => mem_d_out,
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r_rd => mem_rd,
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r_clk_en => '1',
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r_addr => v_dat_i,
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w_d_in => mem_d_in,
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w_wr => mem_we,
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w_clk_en => '1',
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w_addr => adr_i(cpu_adr_width-1 downto cpu_adr_width-v_adr_width)
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);
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v_dat_o_gen: for i in v_dat_o'RANGE generate
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v_dat_o(i) <= mem_d_out(i) and not blank;
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end generate;
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ext_reg_stb <= we_i and stb_i and cyc_i and not mem_stb;
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ext_reg_gen: if (cpu_dat_width < v_dat_width) generate
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ext_reg: wb_out_reg
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generic map (
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width => v_dat_width-cpu_dat_width,
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bus_width => cpu_dat_width,
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offset => 0
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)
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port map (
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clk_i => clk_i,
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rst_i => rst_i,
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cyc_i => cyc_i,
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stb_i => ext_reg_stb,
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we_i => we_i,
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-- ack_o
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adr_i => adr_i(cpu_adr_width-v_adr_width-1 downto 0),
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dat_i => dat_i,
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q => mem_d_in(v_dat_width-cpu_dat_width-1 downto 0)
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);
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end generate;
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dat_o <= dat_oi;
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ack_o <= ( we_i and (stb_i and cyc_i)) or (ack_oi and not (stb_i and cyc_i));
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err_o <= ((not we_i) and (stb_i and cyc_i)) or (err_oi and not (stb_i and cyc_i));
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end wb_pal_ram;
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