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--
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-- File: vga_chip.vhd
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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package constants is
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constant v_dat_width: positive := 16;
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constant v_adr_width : positive := 20;
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constant cpu_dat_width: positive := 32;
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constant cpu_adr_width: positive := 19;
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constant reg_adr_width: positive := 5;
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constant fifo_size: positive := 256;
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-- constant addr_diff: integer := log2(cpu_dat_width/v_dat_width);
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end constants;
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_vga;
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use wb_vga.all;
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use wb_vga.constants.all;
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library wb_tk;
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use wb_tk.all;
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use wb_tk.technology.all;
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-- same as VGA_CORE but without generics. Suited for post-layout simulation.
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entity vga_chip is
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port (
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clk_i: in std_logic;
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clk_en: in std_logic := '1';
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rstn: in std_logic := '1';
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-- CPU bus interface
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data: inout std_logic_vector (cpu_dat_width-1 downto 0) := (others => 'Z');
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addr: in std_logic_vector (cpu_adr_width-1 downto 0) := (others => 'U');
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rdn: in std_logic := '1';
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wrn: in std_logic := '1';
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vmem_cen: in std_logic := '1';
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reg_cen: in std_logic := '1';
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byen: in std_logic_vector ((cpu_dat_width/8)-1 downto 0);
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waitn: out std_logic;
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-- video memory SRAM interface
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s_data : inout std_logic_vector(v_dat_width-1 downto 0);
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s_addr : out std_logic_vector(v_adr_width-1 downto 0);
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s_oen : out std_logic;
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s_wrhn : out std_logic;
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s_wrln : out std_logic;
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s_cen : out std_logic;
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-- sync blank and video signal outputs
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end vga_chip;
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architecture vga_chip of vga_chip is
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component wb_async_slave
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generic (
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width: positive := 16;
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addr_width: positive := 20
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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-- interface for wait-state generator state-machine
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wait_state: in std_logic_vector (3 downto 0);
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-- interface to wishbone master device
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adr_i: in std_logic_vector (addr_width-1 downto 0);
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sel_i: in std_logic_vector ((addr_width/8)-1 downto 0);
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dat_i: in std_logic_vector (width-1 downto 0);
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dat_o: out std_logic_vector (width-1 downto 0);
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dat_oi: in std_logic_vector (width-1 downto 0) := (others => '-');
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we_i: in std_logic;
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stb_i: in std_logic;
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ack_o: out std_logic := '0';
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ack_oi: in std_logic := '-';
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-- interface to async slave
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_addr: out std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_rdn: out std_logic := '1';
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a_wrn: out std_logic := '1';
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a_cen: out std_logic := '1';
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-- byte-enable signals
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a_byen: out std_logic_vector ((width/8)-1 downto 0)
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);
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end component;
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component wb_async_master
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generic (
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width: positive := 16;
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addr_width: positive := 20
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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-- interface to wb slave devices
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s_adr_o: out std_logic_vector (addr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (width-1 downto 0);
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s_dat_o: out std_logic_vector (width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic;
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-- interface to asyncron master device
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a_data: inout std_logic_vector (width-1 downto 0) := (others => 'Z');
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a_addr: in std_logic_vector (addr_width-1 downto 0) := (others => 'U');
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a_rdn: in std_logic := '1';
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a_wrn: in std_logic := '1';
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a_cen: in std_logic := '1';
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a_byen: in std_logic_vector ((width/8)-1 downto 0);
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a_waitn: out std_logic
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);
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end component;
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component vga_core
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generic (
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v_dat_width: positive := 16;
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v_adr_width : positive := 20;
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cpu_dat_width: positive := 16;
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cpu_adr_width: positive := 20;
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reg_adr_width: positive := 20;
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fifo_size: positive := 256
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);
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port (
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clk_i: in std_logic;
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clk_en: in std_logic := '1';
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rst_i: in std_logic := '0';
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-- CPU memory bus interface
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vmem_cyc_i: in std_logic;
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vmem_we_i: in std_logic;
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vmem_stb_i: in std_logic; -- selects video memory
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vmem_ack_o: out std_logic;
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vmem_ack_oi: in std_logic;
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vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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-- CPU register bus interface
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reg_cyc_i: in std_logic;
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reg_we_i: in std_logic;
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reg_stb_i: in std_logic; -- selects configuration registers
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reg_ack_o: out std_logic;
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reg_ack_oi: in std_logic;
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reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0);
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reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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-- video memory interface
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v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
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v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
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v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
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v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
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v_cyc_o: out std_logic;
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v_ack_i: in std_logic;
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v_we_o: out std_logic;
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v_stb_o: out std_logic;
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-- sync blank and video signal outputs
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end component;
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component wb_out_reg
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generic (
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width : positive := 8;
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bus_width: positive := 8;
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offset: integer := 0
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
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cyc_i: in std_logic := '1';
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stb_i: in std_logic;
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sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
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we_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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q: out std_logic_vector (width-1 downto 0)
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);
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end component;
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signal reg_ack_o: std_logic;
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signal reg_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
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signal reg_stb: std_logic;
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signal ws_stb: std_logic;
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signal wait_state: std_logic_vector(3 downto 0);
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signal v_adr_o: std_logic_vector (v_adr_width-1 downto 0);
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signal v_sel_o: std_logic_vector ((v_dat_width/8)-1 downto 0);
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signal v_dat_i: std_logic_vector (v_dat_width-1 downto 0);
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signal v_dat_o: std_logic_vector (v_dat_width-1 downto 0);
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signal v_cyc_o: std_logic;
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signal v_ack_i: std_logic;
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signal v_we_o: std_logic;
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signal v_stb_o: std_logic;
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signal s_byen : std_logic_vector((v_dat_width/8)-1 downto 0);
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signal ws_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
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signal ws_ack_o: std_logic;
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signal s_wrn: std_logic;
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signal dat_i: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_oi: std_logic_vector (cpu_dat_width-1 downto 0);
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signal dat_o: std_logic_vector (cpu_dat_width-1 downto 0);
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signal cyc_i: std_logic;
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signal ack_o: std_logic;
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signal ack_oi: std_logic;
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signal we_i: std_logic;
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signal vmem_stb_i: std_logic;
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signal reg_stb_i: std_logic;
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signal adr_i: std_logic_vector (cpu_adr_width-1 downto 0);
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signal sel_i: std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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signal cen: std_logic;
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signal stb: std_logic;
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signal rst_i: std_logic := '0';
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constant vga_reg_size: integer := size2bits((32*8+cpu_dat_width-1)/cpu_dat_width);
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begin
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rst_i <= not rstn;
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ws_reg: wb_out_reg
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generic map( width => 4, bus_width => cpu_dat_width , offset => 0 )
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port map(
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stb_i => ws_stb,
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q => wait_state,
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rst_val => "1111",
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dat_oi => dat_oi,
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dat_o => ws_dat_o,
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ack_oi => ack_oi,
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ack_o => ws_ack_o,
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adr_i => adr_i(0 downto 0), -- range should be calculated !!!
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sel_i => sel_i, cyc_i => cyc_i, we_i => we_i, clk_i => clk_i, rst_i => rst_i, dat_i => dat_i );
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core : vga_core
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generic map (
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v_dat_width => v_dat_width,
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v_adr_width => v_adr_width,
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cpu_dat_width => cpu_dat_width,
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cpu_adr_width => cpu_adr_width,
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reg_adr_width => reg_adr_width,
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fifo_size => fifo_size
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)
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port map (
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clk_i => clk_i,
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clk_en => clk_en,
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rst_i => rst_i,
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-- CPU bus interface
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vmem_cyc_i => cyc_i,
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vmem_we_i => we_i,
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vmem_stb_i => vmem_stb_i,
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vmem_ack_o => ack_o,
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vmem_ack_oi => reg_ack_o,
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vmem_adr_i => adr_i,
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vmem_sel_i => sel_i,
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vmem_dat_i => dat_i,
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vmem_dat_oi => reg_dat_o,
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vmem_dat_o => dat_o,
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-- CPU register bus interface
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reg_cyc_i => cyc_i,
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reg_we_i => we_i,
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reg_stb_i => reg_stb_i,
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reg_ack_o => reg_ack_o,
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reg_ack_oi => ack_oi,
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reg_adr_i => adr_i(reg_adr_width-1 downto 0),
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reg_sel_i => sel_i,
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reg_dat_i => dat_i,
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reg_dat_oi => dat_oi,
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reg_dat_o => reg_dat_o,
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-- video memory interface
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v_adr_o => v_adr_o,
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v_sel_o => v_sel_o,
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v_dat_i => v_dat_i,
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v_dat_o => v_dat_o,
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v_cyc_o => v_cyc_o,
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v_ack_i => v_ack_i,
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v_we_o => v_we_o,
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v_stb_o => v_stb_o,
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h_sync => h_sync,
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h_blank => h_blank,
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v_sync => v_sync,
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v_blank => v_blank,
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h_tc => h_tc,
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v_tc => v_tc,
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blank => blank,
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video_out => video_out
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);
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mem_driver: wb_async_slave
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generic map (width => v_dat_width, addr_width => v_adr_width)
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port map (
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clk_i => clk_i,
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rst_i => rst_i,
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wait_state => wait_state,
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adr_i => v_adr_o,
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sel_i => v_sel_o,
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dat_o => v_dat_i,
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dat_i => v_dat_o,
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-- dat_oi => (others => '0'),
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we_i => v_we_o,
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stb_i => v_stb_o,
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ack_o => v_ack_i,
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ack_oi => '0',
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a_data => s_data,
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a_addr => s_addr,
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a_rdn => s_oen,
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a_wrn => s_wrn,
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a_cen => s_cen,
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a_byen => s_byen
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);
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s_wrln <= s_wrn or s_byen(0);
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s_wrhn <= s_wrn or s_byen(1);
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master: wb_async_master
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generic map (
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width => cpu_dat_width,
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addr_width => cpu_adr_width
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)
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port map (
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clk_i => clk_i,
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rst_i => rst_i,
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-- interface to wb slave devices
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s_adr_o => adr_i,
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s_sel_o => sel_i,
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s_dat_i => dat_o,
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s_dat_o => dat_i,
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s_cyc_o => cyc_i,
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s_ack_i => ack_o,
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s_err_i => '0',
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s_rty_i => '0',
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s_we_o => we_i,
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s_stb_o => stb,
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-- interface to asyncron master device
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a_data => data,
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a_addr => addr,
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a_rdn => rdn,
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a_wrn => wrn,
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a_cen => cen,
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a_byen => byen,
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a_waitn => waitn
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);
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cen <= vmem_cen and reg_cen;
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vmem_stb_i <= stb and not vmem_cen;
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reg_stb_i <= stb and not reg_cen;
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addr_decoder: process is
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begin
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wait on reg_stb_i, adr_i;
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reg_stb <= '0';
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ws_stb <= '0';
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if (reg_stb_i = '1') then
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case (adr_i(vga_reg_size)) is
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when '0' => reg_stb <= '1';
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when '1' => ws_stb <= '1';
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when others =>
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end case;
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end if;
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end process;
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end vga_chip;
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