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--
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-- File: vga_core.vhd
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.all;
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use wb_tk.technology.all;
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library wb_vga;
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use wb_vga.all;
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entity vga_core is
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generic (
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v_dat_width: positive := 16;
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v_adr_width : positive := 20;
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cpu_dat_width: positive := 16;
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cpu_adr_width: positive := 20;
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reg_adr_width: positive := 20;
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fifo_size: positive := 256
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);
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port (
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clk_i: in std_logic;
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clk_en: in std_logic := '1';
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rst_i: in std_logic := '0';
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-- CPU memory bus interface
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vmem_cyc_i: in std_logic;
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vmem_we_i: in std_logic;
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vmem_stb_i: in std_logic; -- selects video memory
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vmem_ack_o: out std_logic;
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vmem_ack_oi: in std_logic;
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vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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-- CPU register bus interface
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reg_cyc_i: in std_logic;
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reg_we_i: in std_logic;
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reg_stb_i: in std_logic; -- selects configuration registers
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reg_ack_o: out std_logic;
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reg_ack_oi: in std_logic;
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reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0);
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reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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-- video memory interface
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v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
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v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
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v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
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v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
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v_cyc_o: out std_logic;
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v_ack_i: in std_logic;
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v_we_o: out std_logic;
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v_stb_o: out std_logic;
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-- sync blank and video signal outputs
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end vga_core;
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architecture vga_core of vga_core is
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component video_engine
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generic (
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v_mem_width: positive := 16;
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v_addr_width: positive:= 20;
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fifo_size: positive := 256;
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dual_scan_fifo_size: positive := 256
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);
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port (
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clk: in std_logic;
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clk_en: in std_logic := '1';
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reset: in std_logic := '0';
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v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
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v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
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fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
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bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
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multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
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hbs: in std_logic_vector(7 downto 0);
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hss: in std_logic_vector(7 downto 0);
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hse: in std_logic_vector(7 downto 0);
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htotal: in std_logic_vector(7 downto 0);
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vbs: in std_logic_vector(7 downto 0);
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vss: in std_logic_vector(7 downto 0);
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vse: in std_logic_vector(7 downto 0);
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vtotal: in std_logic_vector(7 downto 0);
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pps: in std_logic_vector(7 downto 0);
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high_prior: out std_logic; -- signals to the memory arbitrer to give high
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-- priority to the video engine
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v_mem_rd: out std_logic; -- video memory read request
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v_mem_rdy: in std_logic; -- video memory data ready
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v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
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v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end component video_engine;
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component wb_arbiter
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port (
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-- clk: in std_logic;
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rst_i: in std_logic := '0';
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-- interface to master device a
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a_we_i: in std_logic;
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a_stb_i: in std_logic;
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a_cyc_i: in std_logic;
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a_ack_o: out std_logic;
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a_ack_oi: in std_logic := '-';
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a_err_o: out std_logic;
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a_err_oi: in std_logic := '-';
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a_rty_o: out std_logic;
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a_rty_oi: in std_logic := '-';
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-- interface to master device b
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b_we_i: in std_logic;
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b_stb_i: in std_logic;
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b_cyc_i: in std_logic;
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b_ack_o: out std_logic;
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b_ack_oi: in std_logic := '-';
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b_err_o: out std_logic;
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b_err_oi: in std_logic := '-';
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b_rty_o: out std_logic;
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b_rty_oi: in std_logic := '-';
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-- interface to shared devices
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s_we_o: out std_logic;
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s_stb_o: out std_logic;
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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mux_signal: out std_logic; -- 0: select A signals, 1: select B signals
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-- misc control lines
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priority: in std_logic -- 0: A have priority over B, 1: B have priority over A
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);
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end component;
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component wb_out_reg
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generic (
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width : positive := 8;
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bus_width: positive := 8;
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offset: integer := 0
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
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cyc_i: in std_logic := '1';
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stb_i: in std_logic;
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sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
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we_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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q: out std_logic_vector (width-1 downto 0)
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);
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end component;
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component wb_bus_resize
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generic (
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m_bus_width: positive;
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m_addr_width: positive;
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s_bus_width: positive;
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s_addr_width: positive;
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little_endien: boolean := true -- if set to false, big endien
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);
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port (
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-- clk_i: in std_logic;
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-- rst_i: in std_logic := '0';
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-- Master bus interface
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m_adr_i: in std_logic_vector (m_addr_width-1 downto 0);
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m_sel_i: in std_logic_vector ((m_bus_width/8)-1 downto 0) := (others => '1');
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m_dat_i: in std_logic_vector (m_bus_width-1 downto 0);
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m_dat_oi: in std_logic_vector (m_bus_width-1 downto 0) := (others => '-');
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m_dat_o: out std_logic_vector (m_bus_width-1 downto 0);
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m_cyc_i: in std_logic;
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m_ack_o: out std_logic;
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m_ack_oi: in std_logic := '-';
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m_err_o: out std_logic;
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m_err_oi: in std_logic := '-';
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m_rty_o: out std_logic;
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m_rty_oi: in std_logic := '-';
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m_we_i: in std_logic;
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m_stb_i: in std_logic;
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-- Slave bus interface
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s_adr_o: out std_logic_vector (s_addr_width-1 downto 0);
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s_sel_o: out std_logic_vector ((s_bus_width/8)-1 downto 0);
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s_dat_i: in std_logic_vector (s_bus_width-1 downto 0);
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s_dat_o: out std_logic_vector (s_bus_width-1 downto 0);
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s_cyc_o: out std_logic;
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s_ack_i: in std_logic;
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s_err_i: in std_logic := '-';
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s_rty_i: in std_logic := '-';
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s_we_o: out std_logic;
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s_stb_o: out std_logic
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);
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end component;
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signal v_mem_start: std_logic_vector(v_adr_width-1 downto 0);
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signal v_mem_end: std_logic_vector(v_adr_width-1 downto 0);
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signal reg_bank: std_logic_vector((8*12)-1 downto 0);
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alias fifo_treshold: std_logic_vector(7 downto 0) is reg_bank( 7 downto 0);
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alias bpp: std_logic_vector(1 downto 0) is reg_bank( 9 downto 8);
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alias multi_scan: std_logic_vector(1 downto 0) is reg_bank(13 downto 12);
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alias hbs: std_logic_vector(7 downto 0) is reg_bank(23 downto 16);
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alias hss: std_logic_vector(7 downto 0) is reg_bank(31 downto 24);
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alias hse: std_logic_vector(7 downto 0) is reg_bank(39 downto 32);
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alias htotal: std_logic_vector(7 downto 0) is reg_bank(47 downto 40);
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alias vbs: std_logic_vector(7 downto 0) is reg_bank(55 downto 48);
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alias vss: std_logic_vector(7 downto 0) is reg_bank(63 downto 56);
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alias vse: std_logic_vector(7 downto 0) is reg_bank(71 downto 64);
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alias vtotal: std_logic_vector(7 downto 0) is reg_bank(79 downto 72);
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alias pps: std_logic_vector(7 downto 0) is reg_bank(87 downto 80);
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alias sync_pol: std_logic_vector (3 downto 0) is reg_bank(91 downto 88);
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alias reset_core: std_logic_vector(0 downto 0) is reg_bank(95 downto 95);
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signal v_mem_start_stb: std_logic; -- selects total register
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signal v_mem_end_stb: std_logic; -- selects offset register
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signal reg_bank_stb: std_logic; -- selects all other registers (in a single bank)
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signal reg_bank_do: std_logic_vector(cpu_dat_width-1 downto 0);
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signal v_mem_start_do: std_logic_vector(cpu_dat_width-1 downto 0);
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signal reg_bank_ack: std_logic;
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signal v_mem_start_ack: std_logic;
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signal a_adr_o : std_logic_vector((v_adr_width-1) downto 0);
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signal a_sel_o : std_logic_vector((v_dat_width/8)-1 downto 0);
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signal a_dat_o : std_logic_vector((v_dat_width-1) downto 0);
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signal a_dat_i : std_logic_vector((v_dat_width-1) downto 0);
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signal a_we_o : std_logic;
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signal a_stb_o : std_logic;
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signal a_cyc_o : std_logic;
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signal a_ack_i : std_logic;
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signal b_adr_o : std_logic_vector((v_adr_width-1) downto 0);
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signal b_sel_o : std_logic_vector((v_dat_width/8)-1 downto 0);
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-- signal b_dat_o : std_logic_vector((v_dat_width-1) downto 0);
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signal b_dat_i : std_logic_vector((v_dat_width-1) downto 0);
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signal b_stb_o : std_logic;
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-- signal b_we_o : std_logic;
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-- signal b_cyc_o : std_logic;
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signal b_ack_i : std_logic;
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signal mux_signal: std_logic;
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signal high_prior: std_logic;
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signal reset_engine: std_logic;
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signal i_h_sync: std_logic;
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signal i_h_blank: std_logic;
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signal i_v_sync: std_logic;
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signal i_v_blank: std_logic;
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signal s_wrn : std_logic;
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constant v_adr_zero : std_logic_vector(v_adr_width-1 downto 0) := (others => '0');
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constant reg_bank_rst_val: std_logic_vector(reg_bank'Range) := (others => '0');
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constant reg_bank_size: integer := size2bits((reg_bank'HIGH+cpu_dat_width)/cpu_dat_width);
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constant tot_ofs_size: integer := size2bits((v_adr_width+cpu_dat_width-1)/cpu_dat_width);
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begin
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-- map all registers:
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-- adr_i: in std_logic_vector (max(log2((width+offset+bus_width-1)/bus_width)-1,0) downto 0) := (others => '0');
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reg_bank_reg: wb_out_reg
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generic map( width => reg_bank'HIGH+1, bus_width => cpu_dat_width , offset => 0 )
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port map(
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stb_i => reg_bank_stb,
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q => reg_bank,
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rst_val => reg_bank_rst_val,
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dat_oi => reg_dat_oi,
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dat_o => reg_bank_do,
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ack_oi => reg_ack_oi,
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ack_o => reg_bank_ack,
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adr_i => reg_adr_i(reg_bank_size-1 downto 0),
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sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i );
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v_mem_start_reg: wb_out_reg
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generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 )
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port map(
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stb_i => v_mem_start_stb,
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q => v_mem_start,
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rst_val => v_adr_zero,
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dat_oi => reg_bank_do,
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dat_o => v_mem_start_do,
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ack_oi => reg_bank_ack,
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ack_o => v_mem_start_ack,
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adr_i => reg_adr_i(tot_ofs_size-1 downto 0),
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sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i );
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v_mem_end_reg: wb_out_reg
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generic map( width => v_adr_width, bus_width => cpu_dat_width , offset => 0 )
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port map(
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stb_i => v_mem_end_stb,
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q => v_mem_end,
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rst_val => v_adr_zero,
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dat_oi => v_mem_start_do,
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dat_o => reg_dat_o, -- END OF THE CHAIN
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ack_oi => v_mem_start_ack,
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ack_o => reg_ack_o, -- END OF THE CHAIN
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adr_i => reg_adr_i(tot_ofs_size-1 downto 0),
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sel_i => reg_sel_i, cyc_i => reg_cyc_i, we_i => reg_we_i, clk_i => clk_i, rst_i => rst_i, dat_i => reg_dat_i );
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reset_engine <= rst_i or not reset_core(0);
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v_e: video_engine
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generic map ( v_mem_width => v_dat_width, v_addr_width => v_adr_width, fifo_size => fifo_size, dual_scan_fifo_size => fifo_size )
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port map (
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clk => clk_i,
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clk_en => clk_en,
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reset => reset_engine,
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v_mem_start => v_mem_start,
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v_mem_end => v_mem_end,
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fifo_treshold => fifo_treshold,
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bpp => bpp,
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multi_scan => multi_scan,
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hbs => hbs,
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hss => hss,
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hse => hse,
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htotal => htotal,
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vbs => vbs,
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vss => vss,
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vse => vse,
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vtotal => vtotal,
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pps => pps,
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high_prior => high_prior,
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v_mem_rd => b_stb_o,
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v_mem_rdy => b_ack_i,
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v_mem_addr => b_adr_o,
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v_mem_data => b_dat_i,
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h_sync => i_h_sync,
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h_blank => i_h_blank,
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v_sync => i_v_sync,
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v_blank => i_v_blank,
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h_tc => h_tc,
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v_tc => v_tc,
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blank => blank,
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video_out => video_out
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);
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h_sync <= i_h_sync xor sync_pol(0);
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v_sync <= i_v_sync xor sync_pol(1);
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h_blank <= i_h_blank;-- xor sync_pol(2);
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v_blank <= i_v_blank;-- xor sync_pol(3);
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resize: wb_bus_resize
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generic map (
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m_bus_width => cpu_dat_width, s_bus_width => v_dat_width, m_addr_width => cpu_adr_width, s_addr_width => v_adr_width, little_endien => true
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)
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port map (
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m_adr_i => vmem_adr_i,
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m_cyc_i => vmem_cyc_i,
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m_sel_i => vmem_sel_i,
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m_dat_i => vmem_dat_i,
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m_dat_oi => vmem_dat_oi,
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m_dat_o => vmem_dat_o,
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m_ack_o => vmem_ack_o,
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m_ack_oi => vmem_ack_oi, -- Beginning of the chain
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m_we_i => vmem_we_i,
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m_stb_i => vmem_stb_i,
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s_adr_o => a_adr_o,
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s_sel_o => a_sel_o,
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s_dat_i => a_dat_i,
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s_dat_o => a_dat_o,
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s_cyc_o => a_cyc_o,
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s_ack_i => a_ack_i,
|
|
s_we_o => a_we_o,
|
|
s_stb_o => a_stb_o
|
|
);
|
|
|
|
|
|
arbiter: wb_arbiter
|
|
port map (
|
|
rst_i => reset_engine,
|
|
|
|
a_we_i => a_we_o,
|
|
a_cyc_i => a_cyc_o,
|
|
a_stb_i => a_stb_o,
|
|
a_ack_o => a_ack_i,
|
|
a_ack_oi => '-',
|
|
|
|
b_we_i => '0',
|
|
b_cyc_i => b_stb_o,
|
|
b_stb_i => b_stb_o,
|
|
b_ack_o => b_ack_i,
|
|
b_ack_oi => '0',
|
|
|
|
s_we_o => v_we_o,
|
|
s_stb_o => v_stb_o,
|
|
s_ack_i => v_ack_i,
|
|
s_cyc_o => v_cyc_o,
|
|
|
|
mux_signal => mux_signal,
|
|
|
|
priority => high_prior
|
|
);
|
|
|
|
b_sel_o <= (others => '1');
|
|
|
|
bus_mux: process is
|
|
begin
|
|
wait on mux_signal, v_dat_i, a_adr_o, a_dat_o, b_adr_o, a_sel_o, b_sel_o;
|
|
if (mux_signal = '0') then
|
|
v_adr_o <= a_adr_o;
|
|
v_sel_o <= a_sel_o;
|
|
v_dat_o <= a_dat_o;
|
|
a_dat_i <= v_dat_i;
|
|
b_dat_i <= (others => '-');
|
|
else
|
|
v_adr_o <= b_adr_o;
|
|
v_sel_o <= b_sel_o;
|
|
v_dat_o <= (others => '-');
|
|
b_dat_i <= v_dat_i;
|
|
a_dat_i <= (others => '-');
|
|
end if;
|
|
end process;
|
|
|
|
addr_decoder: process is
|
|
begin
|
|
wait on reg_stb_i, reg_adr_i;
|
|
|
|
v_mem_start_stb <= '0';
|
|
v_mem_end_stb <= '0';
|
|
reg_bank_stb <= '0';
|
|
|
|
if (reg_stb_i = '1') then
|
|
case (reg_adr_i(reg_bank_size)) is
|
|
when '0' =>
|
|
case (reg_adr_i(reg_bank_size-2)) is
|
|
when '0' => v_mem_end_stb <= '1';
|
|
when '1' => v_mem_start_stb <= '1';
|
|
when others =>
|
|
end case;
|
|
when '1' => reg_bank_stb <= '1';
|
|
when others =>
|
|
end case;
|
|
end if;
|
|
end process;
|
|
end vga_core;
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
