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--
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-- File: vga_core_v2.vhd
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/04/26
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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-- vga_core_v2: A WB compatible monitor controller core with version2 features.
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_vga;
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use wb_vga.all;
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library wb_tk;
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use wb_tk.all;
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use wb_tk.technology.all;
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entity vga_core_v2 is
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generic (
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v_dat_width: positive := 16;
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v_adr_width : positive := 20;
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cpu_dat_width: positive := 16;
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cpu_adr_width: positive := 11;
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fifo_size: positive := 256;
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accel_size: positive := 9;
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v_pal_size: positive := 8;
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v_pal_width: positive := 16
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);
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port (
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clk_i: in std_logic;
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clk_en: in std_logic := '1';
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rst_i: in std_logic := '0';
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-- CPU bus interface
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dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic;
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err_o: out std_logic;
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err_oi: in std_logic;
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we_i: in std_logic;
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accel_stb_i: in std_logic;
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pal_stb_i: in std_logic;
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reg_stb_i: in std_logic;
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adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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-- video memory interface
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v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
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v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
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v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
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v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
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v_cyc_o: out std_logic;
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v_ack_i: in std_logic;
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v_we_o: out std_logic;
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v_stb_o: out std_logic;
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-- sync blank and video signal outputs
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (v_pal_size-1 downto 0); -- video output binary signal (unused bits are forced to 0)
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true_color_out: out std_logic_vector (v_pal_width-1 downto 0) -- true-color video output
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);
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end vga_core_v2;
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architecture vga_core_v2 of vga_core_v2 is
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component vga_core
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generic (
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v_dat_width: positive := v_dat_width;
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v_adr_width : positive := v_adr_width;
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cpu_dat_width: positive := cpu_dat_width;
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cpu_adr_width: positive := v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width);
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reg_adr_width: positive := cpu_adr_width;
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fifo_size: positive := fifo_size
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);
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port (
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clk_i: in std_logic;
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clk_en: in std_logic := '1';
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rst_i: in std_logic := '0';
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-- CPU memory bus interface
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vmem_cyc_i: in std_logic;
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vmem_we_i: in std_logic;
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vmem_stb_i: in std_logic; -- selects video memory
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vmem_ack_o: out std_logic;
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vmem_ack_oi: in std_logic;
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vmem_adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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vmem_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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vmem_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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vmem_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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vmem_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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-- CPU register bus interface
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reg_cyc_i: in std_logic;
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reg_we_i: in std_logic;
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reg_stb_i: in std_logic; -- selects configuration registers
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reg_ack_o: out std_logic;
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reg_ack_oi: in std_logic;
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reg_adr_i: in std_logic_vector (reg_adr_width-1 downto 0);
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reg_sel_i: in std_logic_vector ((cpu_dat_width/8)-1 downto 0) := (others => '1');
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reg_dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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reg_dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0);
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reg_dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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-- video memory interface
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v_adr_o: out std_logic_vector (v_adr_width-1 downto 0);
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v_sel_o: out std_logic_vector ((v_dat_width/8)-1 downto 0);
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v_dat_i: in std_logic_vector (v_dat_width-1 downto 0);
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v_dat_o: out std_logic_vector (v_dat_width-1 downto 0);
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v_cyc_o: out std_logic;
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v_ack_i: in std_logic;
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v_we_o: out std_logic;
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v_stb_o: out std_logic;
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-- sync blank and video signal outputs
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end component;
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component accel is
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generic (
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accel_size: positive := accel_size;
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video_addr_width: positive := v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width);
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data_width: positive := cpu_dat_width
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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-- Slave interface to the CPU side
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we_i: in std_logic;
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cyc_i: in std_logic;
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cur_stb_i: in std_logic;
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ext_stb_i: in std_logic;
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acc_stb_i: in std_logic;
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mem_stb_i: in std_logic;
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sel_i: in std_logic_vector ((data_width/8)-1 downto 0) := (others => '1');
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adr_i: in std_logic_vector(accel_size-1 downto 0);
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dat_i: in std_logic_vector(data_width-1 downto 0);
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dat_o: out std_logic_vector(data_width-1 downto 0);
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dat_oi: in std_logic_vector(data_width-1 downto 0);
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ack_o: out std_logic;
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ack_oi: in std_logic;
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-- Master interface to the video memory side.
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v_we_o: out std_logic;
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v_cyc_o: out std_logic;
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v_stb_o: out std_logic;
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v_adr_o: out std_logic_vector (video_addr_width-1 downto 0);
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v_sel_o: out std_logic_vector ((data_width/8)-1 downto 0);
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v_dat_o: out std_logic_vector (data_width-1 downto 0);
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v_dat_i: in std_logic_vector (data_width-1 downto 0);
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v_ack_i: in std_logic
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);
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end component;
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component wb_pal_ram is
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generic (
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cpu_dat_width: positive := cpu_dat_width;
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cpu_adr_width: positive := v_pal_size-bus_resize2adr_bits(cpu_dat_width,v_dat_width);
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v_dat_width: positive := v_pal_width;
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v_adr_width: positive := v_pal_size
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);
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port (
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-- Wishbone interface to CPU (write-only support)
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clk_i: in std_logic;
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rst_i: in std_logic := '0';
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adr_i: in std_logic_vector (cpu_adr_width-1 downto 0);
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dat_i: in std_logic_vector (cpu_dat_width-1 downto 0);
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dat_oi: in std_logic_vector (cpu_dat_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (cpu_dat_width-1 downto 0);
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cyc_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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err_o: out std_logic;
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err_oi: in std_logic := '-';
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we_i: in std_logic;
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stb_i: in std_logic;
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-- Interface to the video output
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blank: in std_logic;
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v_dat_i: in std_logic_vector(v_adr_width-1 downto 0);
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v_dat_o: out std_logic_vector(v_dat_width-1 downto 0)
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);
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end component;
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-- register select signals
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signal vga_reg_stb: std_logic;
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signal cur_stb: std_logic;
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signal ext_stb: std_logic;
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-- accelerator select signals
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signal acc_stb: std_logic;
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signal mem_stb: std_logic;
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signal vga_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
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signal vga_ack_o: std_logic;
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signal vreg_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
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signal vreg_ack_o: std_logic;
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signal accel_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
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signal accel_ack_o: std_logic;
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signal pal_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
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signal pal_ack_o: std_logic;
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signal i_video_out: std_logic_vector (v_pal_size-1 downto 0);
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signal i_blank: std_logic;
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signal vmem_stb: std_logic;
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signal vm_cyc: std_logic;
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signal vm_we: std_logic;
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signal vm_stb: std_logic;
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signal vm_ack: std_logic;
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signal vm_adr: std_logic_vector(v_adr_width-bus_resize2adr_bits(cpu_dat_width,v_dat_width)-1 downto 0);
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signal vm_sel: std_logic_vector(cpu_dat_width/8-1 downto 0);
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signal vm_dat_i: std_logic_vector(cpu_dat_width-1 downto 0);
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signal vm_dat_o: std_logic_vector(cpu_dat_width-1 downto 0);
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constant vga_reg_size: integer := size2bits((32*8)/cpu_dat_width)-1;
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begin
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core : vga_core
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port map (
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clk_i => clk_i,
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clk_en => clk_en,
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rst_i => rst_i,
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-- CPU bus interface
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vmem_cyc_i => vm_cyc,
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vmem_we_i => vm_we,
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vmem_stb_i => vm_stb,
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vmem_ack_o => vm_ack,
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vmem_ack_oi => '1',
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vmem_adr_i => vm_adr,
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vmem_sel_i => vm_sel,
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vmem_dat_i => vm_dat_i,
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vmem_dat_oi => (cpu_dat_width-1 downto 0 => '-'),
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vmem_dat_o => vm_dat_o,
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-- CPU register bus interface
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reg_cyc_i => cyc_i,
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reg_we_i => we_i,
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reg_stb_i => vga_reg_stb,
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reg_ack_o => vreg_ack_o,
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reg_ack_oi => ack_oi,
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reg_adr_i => adr_i,
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reg_sel_i => sel_i,
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reg_dat_i => dat_i,
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reg_dat_oi => dat_oi,
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reg_dat_o => vreg_dat_o,
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-- video memory interface
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v_adr_o => v_adr_o,
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v_sel_o => v_sel_o,
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v_dat_i => v_dat_i,
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v_dat_o => v_dat_o,
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v_cyc_o => v_cyc_o,
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v_ack_i => v_ack_i,
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v_we_o => v_we_o,
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v_stb_o => v_stb_o,
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h_sync => h_sync,
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h_blank => h_blank,
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v_sync => v_sync,
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v_blank => v_blank,
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h_tc => h_tc,
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v_tc => v_tc,
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blank => i_blank,
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video_out => i_video_out
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);
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acc: accel
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port map (
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clk_i => clk_i,
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rst_i => rst_i,
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-- Slave interface to the CPU side
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we_i => we_i,
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cyc_i => cyc_i,
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cur_stb_i => cur_stb,
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ext_stb_i => ext_stb,
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acc_stb_i => acc_stb,
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mem_stb_i => mem_stb,
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sel_i => sel_i,
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adr_i => adr_i(accel_size-1 downto 0),
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dat_i => dat_i,
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dat_o => accel_dat_o,
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dat_oi => vreg_dat_o,
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ack_o => accel_ack_o,
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ack_oi => vreg_ack_o,
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-- Master interface to the video memory side.
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v_we_o => vm_we,
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v_cyc_o => vm_cyc,
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v_stb_o => vm_stb,
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v_adr_o => vm_adr,
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v_sel_o => vm_sel,
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v_dat_o => vm_dat_i,
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v_dat_i => vm_dat_o,
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v_ack_i => vm_ack
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);
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palette: wb_pal_ram
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port map (
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clk_i => clk_i,
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rst_i => rst_i,
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adr_i => adr_i(v_pal_size-bus_resize2adr_bits(cpu_dat_width,v_dat_width)-1 downto 0),
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dat_i => dat_i,
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dat_oi => accel_dat_o,
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dat_o => dat_o,
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cyc_i => cyc_i,
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ack_o => ack_o,
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ack_oi => accel_ack_o,
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err_o => err_o,
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err_oi => err_oi,
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we_i => we_i,
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stb_i => pal_stb_i,
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-- Interface to the video output
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blank => i_blank,
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v_dat_i => i_video_out,
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v_dat_o => true_color_out
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);
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video_out <= i_video_out;
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blank <= i_blank;
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reg_addr_decoder: process is
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begin
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wait on reg_stb_i, adr_i;
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vga_reg_stb <= '0';
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cur_stb <= '0';
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ext_stb <= '0';
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if (reg_stb_i = '1') then
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case (adr_i(vga_reg_size)) is
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when '0' => vga_reg_stb <= '1';
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when '1' =>
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if (adr_i(vga_reg_size-2) = '1') then
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case (adr_i(vga_reg_size-3)) is
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when '0' => cur_stb <= '1';
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when '1' => ext_stb <= '1';
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when others =>
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end case;
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end if;
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when others =>
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end case;
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end if;
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end process;
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accel_addr_decoder: process is
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begin
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wait on accel_stb_i, adr_i;
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acc_stb <= '0';
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mem_stb <= '0';
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if (accel_stb_i = '1') then
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case (adr_i(accel_size)) is
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when '0' => acc_stb <= '1';
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when '1' => mem_stb <= '1';
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when others =>
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end case;
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end if;
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end process;
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end vga_core_v2;
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