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--
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-- File: video_engine.vhd
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity video_engine is
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generic (
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v_mem_width: positive := 16;
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v_addr_width: positive:= 20;
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fifo_size: positive := 256;
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dual_scan_fifo_size: positive := 256
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);
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port (
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clk: in std_logic;
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clk_en: in std_logic := '1';
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reset: in std_logic := '0';
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v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
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v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
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fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
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bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
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multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
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hbs: in std_logic_vector(7 downto 0);
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hss: in std_logic_vector(7 downto 0);
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hse: in std_logic_vector(7 downto 0);
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htotal: in std_logic_vector(7 downto 0);
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vbs: in std_logic_vector(7 downto 0);
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vss: in std_logic_vector(7 downto 0);
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vse: in std_logic_vector(7 downto 0);
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vtotal: in std_logic_vector(7 downto 0);
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pps: in std_logic_vector(7 downto 0);
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high_prior: out std_logic; -- signals to the memory arbitrer to give high
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-- priority to the video engine
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v_mem_rd: out std_logic; -- video memory read request
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v_mem_rdy: in std_logic; -- video memory data ready
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v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
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v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic;
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end video_engine;
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architecture video_engine of video_engine is
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component hv_sync
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port (
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clk: in std_logic;
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pix_clk_en: in std_logic := '1';
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reset: in std_logic := '0';
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hbs: in std_logic_vector(7 downto 0);
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hss: in std_logic_vector(7 downto 0);
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hse: in std_logic_vector(7 downto 0);
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htotal: in std_logic_vector(7 downto 0);
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vbs: in std_logic_vector(7 downto 0);
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vss: in std_logic_vector(7 downto 0);
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vse: in std_logic_vector(7 downto 0);
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vtotal: in std_logic_vector(7 downto 0);
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h_sync: out std_logic;
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h_blank: out std_logic;
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v_sync: out std_logic;
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v_blank: out std_logic;
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h_tc: out std_logic;
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v_tc: out std_logic;
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blank: out std_logic
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);
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end component;
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component mem_reader
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generic (
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v_mem_width: positive := 16;
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v_addr_width: positive:= 20;
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fifo_size: positive := 256;
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dual_scan_fifo_size: positive := 256
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);
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port (
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clk: in std_logic;
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clk_en: in std_logic;
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pix_clk_en: in std_logic;
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reset: in std_logic := '0';
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v_mem_end: in std_logic_vector(v_addr_width-1 downto 0); -- video memory end address in words
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v_mem_start: in std_logic_vector(v_addr_width-1 downto 0) := (others => '0'); -- video memory start adderss in words
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fifo_treshold: in std_logic_vector(7 downto 0); -- priority change threshold
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bpp: in std_logic_vector(1 downto 0); -- number of bits makes up a pixel valid values: 1,2,4,8
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multi_scan: in std_logic_vector(1 downto 0); -- number of repeated scans
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high_prior: out std_logic; -- signals to the memory arbitrer to give high
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-- priority to the video engine
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v_mem_rd: out std_logic; -- video memory read request
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v_mem_rdy: in std_logic; -- video memory data ready
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v_mem_addr: out std_logic_vector (v_addr_width-1 downto 0); -- video memory address
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v_mem_data: in std_logic_vector (v_mem_width-1 downto 0); -- video memory data
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blank: in std_logic; -- video sync generator blank output
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h_tc: in std_logic; -- horizontal sync pulse. Must be 1 clock wide!
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video_out: out std_logic_vector (7 downto 0) -- video output binary signal (unused bits are forced to 0)
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);
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end component;
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signal pix_clk_en: std_logic;
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signal i_h_sync: std_logic;
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signal i_h_blank: std_logic;
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signal i_v_sync: std_logic;
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signal i_v_blank: std_logic;
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signal i_h_tc: std_logic;
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signal i_v_tc: std_logic;
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signal i_blank: std_logic;
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begin
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pps_gen: process is
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variable cnt: std_logic_vector(3 downto 0);
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begin
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wait until clk'EVENT and clk = '1';
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if (reset = '1') then
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cnt := (others => '0');
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pix_clk_en <= '0';
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else
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if (clk_en = '0') then
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pix_clk_en <= '0';
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else
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if (cnt = pps(3 downto 0)) then
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cnt := (others => '0');
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pix_clk_en <= '1';
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else
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cnt := add_one(cnt);
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pix_clk_en <= '0';
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end if;
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end if;
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end if;
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end process;
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mem_engine : mem_reader
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generic map (
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v_mem_width => v_mem_width,
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v_addr_width => v_addr_width,
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fifo_size => fifo_size,
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dual_scan_fifo_size => dual_scan_fifo_size
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)
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port map (
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clk => clk,
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clk_en => clk_en,
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pix_clk_en => pix_clk_en,
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reset => reset,
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v_mem_end => v_mem_end,
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v_mem_start => v_mem_start,
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fifo_treshold => fifo_treshold,
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bpp => bpp,
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multi_scan => multi_scan,
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high_prior => high_prior,
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v_mem_rd => v_mem_rd,
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v_mem_rdy => v_mem_rdy,
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v_mem_addr => v_mem_addr,
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v_mem_data => v_mem_data,
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blank => i_blank,
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h_tc => i_h_tc,
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video_out => video_out
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);
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sync_engine : hv_sync
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port map (
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clk => clk,
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pix_clk_en => pix_clk_en,
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reset => reset,
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hbs => hbs,
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hss => hss,
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hse => hse,
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htotal => htotal,
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vbs => vbs,
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vss => vss,
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vse => vse,
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vtotal => vtotal,
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h_sync => i_h_sync,
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h_blank => i_h_blank,
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v_sync => i_v_sync,
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v_blank => i_v_blank,
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h_tc => i_h_tc,
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v_tc => i_v_tc,
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blank => i_blank
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);
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-- Delay all sync signals with one pixel. That's becouse of the syncron output of the mem_reader
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sync_delay: process is
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begin
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wait until (clk'EVENT and clk='1');
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if (reset = '1') then
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h_sync <= '0';
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h_blank <= '1';
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v_sync <= '0';
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v_blank <= '1';
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blank <= '1';
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elsif (pix_clk_en = '1') then
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h_sync <= i_h_sync;
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h_blank <= i_h_blank;
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v_sync <= i_v_sync;
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v_blank <= i_v_blank;
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blank <= i_blank;
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end if;
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end process;
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h_tc <= i_h_tc;
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v_tc <= i_v_tc;
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end video_engine;
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No newline at end of file
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No newline at end of file
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