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--
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-- Wishbone bus toolkit.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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--
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-- ELEMENTS:
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-- wb_io_reg: A slightly modified version of the wb_out_reg component
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-------------------------------------------------------------------------------
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--
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-- wb_io_reg. A slightly modified version of the wb_out_reg component
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--
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library wb_tk;
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use wb_tk.technology.all;
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entity wb_io_reg is
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generic (
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width : positive := 8;
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bus_width: positive := 8;
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offset: integer := 0
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);
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port (
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_val: std_logic_vector(width-1 downto 0) := (others => '0');
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cyc_i: in std_logic := '1';
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stb_i: in std_logic;
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sel_i: in std_logic_vector ((bus_width/8)-1 downto 0) := (others => '1');
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we_i: in std_logic;
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ack_o: out std_logic;
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ack_oi: in std_logic := '-';
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adr_i: in std_logic_vector (size2bits((width+offset+bus_width-1)/bus_width)-1 downto 0) := (others => '0');
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dat_i: in std_logic_vector (bus_width-1 downto 0);
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dat_oi: in std_logic_vector (bus_width-1 downto 0) := (others => '-');
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dat_o: out std_logic_vector (bus_width-1 downto 0);
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q: out std_logic_vector (width-1 downto 0);
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ext_d: in std_logic_vector (width-1 downto 0) := (others => '-');
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ext_we: in std_logic := '0'
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);
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end wb_io_reg;
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architecture wb_io_reg of wb_io_reg is
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signal content : std_logic_vector (width-1 downto 0);
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begin
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-- output bus handling with logic
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gen_dat_o: process is
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variable rd_sel: std_logic;
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variable adr: integer;
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variable reg_i: integer;
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begin
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wait on dat_oi, we_i, stb_i, content, adr_i, cyc_i, sel_i;
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rd_sel := cyc_i and stb_i and not we_i;
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for i in dat_i'RANGE loop
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adr := CONV_INTEGER(adr_i);
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reg_i := i-offset+adr*bus_width;
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if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then
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dat_o(i) <= (dat_oi(i) and not rd_sel) or (content(reg_i) and rd_sel);
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else
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dat_o(i) <= dat_oi(i);
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end if;
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end loop;
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end process;
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-- this item never generates any wait-states unless an external write is under process
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-- ack_o <= (stb_i or ack_oi) and (not (ext_we and we_i));
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ack_o <= (ack_oi and not stb_i) or ((not (ext_we and we_i)) and stb_i);
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-- ack_o <= (stb_i or ack_oi);
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reg: process is
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variable adr: integer;
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variable reg_i: integer;
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begin
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wait until clk_i'EVENT and clk_i='1';
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if (rst_i = '1') then
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content <= rst_val;
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else
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if (ext_we = '1') then
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content <= ext_d;
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else
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if (stb_i = '1' and cyc_i = '1' and we_i = '1') then
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for i in dat_i'RANGE loop
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adr := CONV_INTEGER(adr_i);
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reg_i := i-offset+adr*bus_width;
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if ((reg_i >= 0) and (reg_i < width) and (sel_i(i/8) = '1')) then
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content(reg_i) <= dat_i(i);
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end if;
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end loop;
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end if;
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end if;
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end if;
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end process;
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q <= content;
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end wb_io_reg;
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