| Line 38... |
Line 38... |
#include <stdio.h>
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#include <stdio.h>
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#include <assert.h>
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#include <assert.h>
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#define PREFIX "DDR3-SDRAM"
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#define PREFIX "DDR3-SDRAM"
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const unsigned ckCL = 5,
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const unsigned ckCL = 5,
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ckRC = 3,
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ckRC = 10,
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ckRAS = 7,
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ckRFC = 320, // Clocks from refresh to activate
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ckRFC = 320, // Clocks from refresh to activate
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nREF = 4,
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ckREFI = 1560; // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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/*
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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const unsigned nREF = 4,
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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*/
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const unsigned nREF = 1,
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ckREFIn = ckREFI;
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#include "ddrsdramsim.h"
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#include "ddrsdramsim.h"
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BANKINFO::BANKINFO(void) {
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m_state = 0; m_row = 0; m_wcounter = 0; m_min_time_before_precharge=0;
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}
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void BANKINFO::tick(int cmd, unsigned addr) {
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void BANKINFO::tick(int cmd, unsigned addr) {
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if (m_wcounter)
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if (m_wcounter)
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m_wcounter--;
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m_wcounter--;
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switch(cmd) {
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switch(cmd) {
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case DDR_REFRESH:
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assert(m_state == 0);
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break;
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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m_state = 6;
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m_state = 6;
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// While the specification allows precharging an already
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// While the specification allows precharging an already
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// precharged bank, we can keep that from happening
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// precharged bank, we can keep that from happening
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// here:
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// here:
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// assert(m_state&7);
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// assert(m_state&7);
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// Only problem is, this will currently break our
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// Only problem is, this will currently break our
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// refresh logic.
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// refresh logic.
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if (m_min_time_before_precharge != 0) {
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printf("BANK-FAIL: TIME-BEFORE-PRECHARGE = %d (should be zero)\n", m_min_time_before_precharge);
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assert(m_min_time_before_precharge == 0);
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} if (m_min_time_before_activate != 0) {
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printf("BANK-FAIL: TIME-BEFORE-ACTIVATE = %d (should be zero)\n", m_min_time_before_activate);
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assert(m_min_time_before_activate==0);
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}
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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if (((m_state&7)!=0)&&((addr&0x7fff) != m_row)) {
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printf("BANK-FAIL: Attempt to Activate an already active bank without closing it first (m_state = %x)\n", m_state);
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assert((m_state&7)==0);
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}
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if (m_wcounter != 0) {
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printf("BANK-FAIL: ACTIVATE too soon after write (wcounter = %d)\n", m_wcounter);
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assert(m_wcounter == 0);
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assert(m_wcounter == 0);
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} if (m_min_time_before_activate!=0) {
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printf("BANK-FAIL: ACTIVATE too soon after last activate, (ctr=%d)\n", m_min_time_before_activate);
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assert(m_min_time_before_activate==0);
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}
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m_state = 1;
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m_state = 1;
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m_row = addr & 0x7fff;
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m_row = addr & 0x7fff;
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m_min_time_before_precharge = ckRAS;
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m_min_time_before_activate = ckRC;
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break;
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break;
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case DDR_READ: case DDR_WRITE:
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case DDR_READ: case DDR_WRITE:
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if (DDR_READ)
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if (DDR_READ)
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assert(m_wcounter == 0);
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assert(m_wcounter == 0);
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else
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else
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m_wcounter = 3+4+4;
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m_wcounter = 3+4+4;
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printf("BANK::R/W Request, m_state = %d\n", m_state);
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assert((m_state&7) == 7);
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assert((m_state&7) == 7);
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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break;
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break;
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case DDR_ZQS:
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case DDR_ZQS:
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assert((m_state&7) == 0);
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assert((m_state&7) == 0);
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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break;
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break;
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case DDR_NOOP:
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case DDR_NOOP:
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m_state <<= 1;
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m_state <<= 1;
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m_state |= (m_state&2)>>1;
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m_state |= (m_state&2)>>1;
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m_state &= 0x0f;
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if (m_min_time_before_precharge)
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m_min_time_before_precharge--;
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if (m_min_time_before_activate)
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m_min_time_before_activate--;
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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}
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}
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| Line 133... |
Line 177... |
if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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assert(m_reset_counts > 147);
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assert(m_reset_counts > 147);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 3;
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m_reset_state = 3;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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// Set MR2
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assert(ba == 2);
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assert(ba == 2);
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assert(addr == 0x040);
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assert(addr == 0x040);
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} break;
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} break;
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case 3:
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case 3:
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m_reset_counts++;
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m_reset_counts++;
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| Line 144... |
Line 189... |
if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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// assert(m_reset_counts > 3);
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// assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 4;
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m_reset_state = 4;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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// assert(ba == 1);
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// Set MR1
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// assert(addr == 0x847);
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assert(ba == 1);
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assert(addr == 0x844);
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} break;
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} break;
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case 4:
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case 4:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf(PREFIX "::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf(PREFIX "::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 5;
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m_reset_state = 5;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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// Set MR0
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assert(ba == 0);
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assert(ba == 0);
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assert(addr == 0x210);
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assert(addr == 0x210);
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} break;
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} break;
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case 5:
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case 5:
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m_reset_counts++;
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m_reset_counts++;
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| Line 209... |
Line 256... |
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gbl_state = m_reset_state;
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gbl_state = m_reset_state;
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gbl_counts= m_reset_counts;
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gbl_counts= m_reset_counts;
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m_nrefresh_issued = nREF;
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m_nrefresh_issued = nREF;
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m_clocks_since_refresh++;
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m_clocks_since_refresh++;
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(cmd, 0);
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} else if (!cke) {
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} else if (!cke) {
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assert(0&&"Clock not enabled!");
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assert(0&&"Clock not enabled!");
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} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
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} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
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if (DDR_REFRESH == cmd) {
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if (DDR_REFRESH == cmd) {
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m_clocks_since_refresh = 0;
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m_clocks_since_refresh = 0;
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| Line 223... |
Line 272... |
} else {
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} else {
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m_clocks_since_refresh++;
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m_clocks_since_refresh++;
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assert(DDR_NOOP == cmd);
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assert(DDR_NOOP == cmd);
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}
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}
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_REFRESH,0);
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m_bank[i].tick(cmd,0);
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if (m_nrefresh_issued == nREF)
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if (m_nrefresh_issued == nREF)
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printf(PREFIX "::Refresh cycle complete\n");
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printf(PREFIX "::Refresh cycle complete\n");
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} else {
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} else {
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// In operational mode!!
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// In operational mode!!
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| Line 245... |
Line 294... |
m_bank[i].tick(DDR_REFRESH,0);
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m_bank[i].tick(DDR_REFRESH,0);
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m_clocks_since_refresh = 0;
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m_clocks_since_refresh = 0;
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assert(0 && "Internal err: Refresh should be handled above");
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assert(0 && "Internal err: Refresh should be handled above");
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break;
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break;
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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if (addr & 0x40) {
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if (addr & 0x400) {
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// Precharge all
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// Precharge all
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_PRECHARGE,0);
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m_bank[i].tick(DDR_PRECHARGE,0);
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} else {
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} else {
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m_bank[ba].tick(DDR_PRECHARGE,0);
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m_bank[ba].tick(DDR_PRECHARGE,0);
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| Line 258... |
Line 307... |
m_bank[i].tick(DDR_NOOP,0);
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m_bank[i].tick(DDR_NOOP,0);
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}
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}
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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assert(m_clocks_since_refresh >= (int)ckRFC);
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assert(m_clocks_since_refresh >= (int)ckRFC);
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printf(PREFIX "::Activating bank %d, address %08x\n", ba, addr);
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m_bank[ba].tick(DDR_ACTIVATE,addr);
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m_bank[ba].tick(DDR_ACTIVATE,addr);
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
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if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
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break;
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break;
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case DDR_WRITE:
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case DDR_WRITE:
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| Line 356... |
Line 406... |
for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_NOOP,addr);
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m_bank[i].tick(DDR_NOOP,addr);
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break;
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break;
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}
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}
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if (true) {
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if (false) {
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bool flag = false;
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bool flag = false;
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for(int i=0; i<5; i++) {
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for(int i=0; i<5; i++) {
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int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
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int bl = (m_busloc+1+i)&(NTIMESLOTS-1);
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nxtts = &m_bus[bl];
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nxtts = &m_bus[bl];
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if (nxtts->m_used) {
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if (nxtts->m_used) {
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