////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: wbfmtxhack.v
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// Filename: wbfmtxhack.v
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//
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//
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// Project: A Wishbone Controlled FM Transmitter Hack
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// Project: A Wishbone Controlled FM Transmitter Hack
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//
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//
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// Purpose: This Hack is based off of two things: 1) the interface spec
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// Purpose: This Hack is based off of two things: 1) the interface spec
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// of the WB controlled PWM audio device, and 2) a Raspberry Pi
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// of the WB controlled PWM audio device, and 2) a Raspberry Pi
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// Hack I was shown that converted the RPi PWM device into an FM
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// Hack I was shown that converted the RPi PWM device into an FM
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// transmitter. So, the question is, can a GPIO pin be turned into an
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// transmitter. So, the question is, can a GPIO pin be turned into an
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// FM transmitter that can be heard throughout the house?
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// FM transmitter that can be heard throughout the house?
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//
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//
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// We'll try and do this properly: We'll use a Numerically Controlled
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// We'll try and do this properly: We'll use a Numerically Controlled
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// Oscillator to generate our signal, but only grab the top bit out of
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// Oscillator to generate our signal, but only grab the top bit out of
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// that oscillator. We'll then send this bit to the GPIO pin (a.k.a.
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// that oscillator. We'll then send this bit to the GPIO pin (a.k.a.
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// antenna) to see if it can accomplish our goals.
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// antenna) to see if it can accomplish our goals.
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//
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//
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// WB Control/Registers:
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// WB Control/Registers:
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// 1'b0: Next Sample
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// 1'b0: Next Sample
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//
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//
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// The top bits of this 'next sample' will indicate the number
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// The top bits of this 'next sample' will indicate the number
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// of clock ticks before we generate a need next sample interrupt.
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// of clock ticks before we generate a need next sample interrupt.
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// If these top bits are zero, the sample rate will not be
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// If these top bits are zero, the sample rate will not be
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// adjusted. The value to set here is the value of the clock
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// adjusted. The value to set here is the value of the clock
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// rate divided by the desired sample rate. Hence, if the clock
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// rate divided by the desired sample rate. Hence, if the clock
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// rate is 80MHz, setting this to 10e3 (unsigned) would set us up
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// rate is 80MHz, setting this to 10e3 (unsigned) would set us up
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// for an 8kHz sample rate, whereas setting these upper 16 bits to
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// for an 8kHz sample rate, whereas setting these upper 16 bits to
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// 1814 would specify a sample rate closer to 44.1kHz.
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// 1814 would specify a sample rate closer to 44.1kHz.
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//
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//
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// The lower 16 bits specify the value of the next sample.
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// The lower 16 bits specify the value of the next sample.
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//
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//
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// Since we'll be dealing with FM modulation, we'll try to arrange
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// Since we'll be dealing with FM modulation, we'll try to arrange
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// that this sixteen bit sample will correspond to a maximum
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// that this sixteen bit sample will correspond to a maximum
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// FM deviation of about 75 kHz.
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// FM deviation of about 75 kHz.
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//
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//
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//
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//
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// 1'b1: The Oscillator "Frequency" (really stepsize). This should be
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// 1'b1: The Oscillator "Frequency" (really stepsize). This should be
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// used to control/determine the "RF frequency" this device can
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// used to control/determine the "RF frequency" this device can
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// transmit on.
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// transmit on.
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//
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//
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// To transmit at 0Hz, set this to zero. To transmit at
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// To transmit at 0Hz, set this to zero. To transmit at
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// CLKSPEED/2 Hz, set this to 32'h8000_0000. Hence for a
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// CLKSPEED/2 Hz, set this to 32'h8000_0000. Hence for a
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// transmit frequency of X, set this value to
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// transmit frequency of X, set this value to
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//
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//
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// OSXFREQ = 2^32 * X / CLKSPEED
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// OSXFREQ = 2^32 * X / CLKSPEED
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//
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//
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// Where X and CLKSPEED share the same units. But how shall we
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// Where X and CLKSPEED share the same units. But how shall we
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// transmit at speeds of anything higher than CLKSPEED/2? By
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// transmit at speeds of anything higher than CLKSPEED/2? By
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// aliasing up. Hence, set X to your actual frequency value,
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// aliasing up. Hence, set X to your actual frequency value,
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// divide by the clockspeed and multiply by 2^32. Remove any
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// divide by the clockspeed and multiply by 2^32. Remove any
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// bits that don't fit in the top 32 and you are there.
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// bits that don't fit in the top 32 and you are there.
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//
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//
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// This also gives us about 20 mHz resolution for our Carrier
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// This also gives us about 20 mHz resolution for our Carrier
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// frequency--overkill perhaps, but it should work.
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// frequency--overkill perhaps, but it should work.
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//
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//
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// So ... how do we create our 75 kHz deviation? We want:
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// So ... how do we create our 75 kHz deviation? We want:
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//
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//
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// MAX_STEPSIZE = 2^32 * (X + 75kHz * sample / 2^15) / CLKSPEED
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// MAX_STEPSIZE = 2^32 * (X + 75kHz * sample / 2^15) / CLKSPEED
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// = OSXFREQ = (2^32 * sample / 2^15 / CLKSPEED * 75 kHz)
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// = OSXFREQ = (2^32 * sample / 2^15 / CLKSPEED * 75 kHz)
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// = 123 * sample ~= 128 * sample = sample << 7.
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// = 123 * sample ~= 128 * sample = sample << 7.
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//
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//
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// Thus, by shifting our input sample value a touch, we can multiply by
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// Thus, by shifting our input sample value a touch, we can multiply by
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// nearly the exact constant we want.
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// nearly the exact constant we want.
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//
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//
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// OSERDES:
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// Okay, the first version was fun and worked ... okay, but ... can we do
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// better? I mean, we lost over 10dB by undersampling, and most(many?)
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// FPGA's have OSERDES components that will allow bits to toggle faster
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// than the FPGA clock rate. In other words, if we have an 80MHz clock,
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// we should be able to output samples at 320MHz, no?
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//
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// Let's do even one better than that: suppose we create outputs for a
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// 2-bit DAC. Of course, our chip doesn't have a 2-bit DAC, much less a
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// DAC at all, but could we create one from our I/O pins? For example,
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// if two I/O pins both produced a 1, the resulting field would be
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// stronger, right? What if they both produced a zero, same thing, right?
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// Now, what if one produced a 1 and one produced a 0? Would the fields
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// interfere with each other? You know, would they produce a sum field
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// that was better than just the one-bit produced field? Perhaps, with
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// only a 1-bit output, we get +/- 3. With a two bit output, we should
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// be able to get { -3, 0, 3 }, right? (Ignore scaling ...)
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//
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// A better two-bit output would probably be something like
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// { -3, -1, 1, 3 }. How can we produce something like that? Without a
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// proper ADC? Can we connect a majority of the pins to the high order
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// bit output, and some fewer number to the low order bit output?
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// Would this create a better field?
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//
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// The component created with `define OSERDES is designed to allow such
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// hypotheses to be tested.
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// You should have received a copy of the GNU General Public License along
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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// <http://www.gnu.org/licenses/> for a copy.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbfmtxhack(i_clk,
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module wbfmtxhack(i_clk,
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// Wishbone interface
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_tx, o_int);
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o_tx, o_int);
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parameter DEFAULT_RELOAD = 16'd1814; // 44.1kHz at a 80MHz clock
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parameter DEFAULT_RELOAD = 16'd1814; // 44.1kHz at a 80MHz clock
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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output reg o_wb_ack;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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`ifdef USE_OSERDES
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output wire [7:0] o_tx;
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`else
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output wire o_tx;
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output wire o_tx;
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`endif
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output reg o_int;
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output reg o_int;
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reg [31:0] nco_step, nco_phase;
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reg [31:0] nco_step;
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// How often shall we create an interrupt? Every reload_value clocks!
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// How often shall we create an interrupt? Every reload_value clocks!
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// If VARIABLE_RATE==0, this value will never change and will be kept
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// at the default reload rate (44.1 kHz, for a 100 MHz clock)
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// at the default reload rate (44.1 kHz, for a 100 MHz clock)
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reg [15:0] reload_value;
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reg [15:0] reload_value;
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initial reload_value = DEFAULT_RELOAD;
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initial reload_value = DEFAULT_RELOAD;
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// Data write, but we use the upper 16 bits to set our sample rate.
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// Data write, but we use the upper 16 bits to set our sample rate.
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// If these bits are zero, we ignore the write--allowing users to
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// If these bits are zero, we ignore the write--allowing users to
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// write samples without adjusting the sample rate.
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// write samples without adjusting the sample rate.
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always @(posedge i_clk) // Set sample rate
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always @(posedge i_clk) // Set sample rate
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr)&&(i_wb_we)
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if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr)&&(i_wb_we)
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&&(|i_wb_data[31:16]))
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&&(|i_wb_data[31:16]))
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reload_value <= i_wb_data[31:16];
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reload_value <= i_wb_data[31:16];
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// Set the NCO transmit frequency
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// Set the NCO transmit frequency
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initial nco_step = 32'h00;
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initial nco_step = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
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nco_step <= i_wb_data[31:0];
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nco_step <= i_wb_data[31:0];
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reg ztimer;
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reg ztimer;
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reg [15:0] timer;
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reg [15:0] timer;
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initial ztimer = 1'b0;
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initial ztimer = 1'b0;
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always @(posedge i_clk) // Be true when the timer is zero
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always @(posedge i_clk) // Be true when the timer is zero
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ztimer <= (timer[15:0] == 16'h1);
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ztimer <= (timer[15:0] == 16'h1);
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initial timer = reload_value;
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initial timer = reload_value;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (ztimer)
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if (ztimer)
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timer <= reload_value;
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timer <= reload_value;
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else
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else
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timer <= timer - 16'h1;
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timer <= timer - 16'h1;
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reg [15:0] next_sample, sample_out;
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reg [15:0] next_sample, sample_out;
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initial sample_out = 16'h00;
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initial sample_out = 16'h00;
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initial next_sample = 16'h00;
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initial next_sample = 16'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (ztimer)
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if (ztimer)
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sample_out <= next_sample;
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sample_out <= next_sample;
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reg next_valid;
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reg next_valid;
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initial next_valid = 1'b1;
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initial next_valid = 1'b1;
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initial next_sample = 16'h8000;
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initial next_sample = 16'h8000;
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always @(posedge i_clk) // Data write
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always @(posedge i_clk) // Data write
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr))
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if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr))
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begin
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begin
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// Write with two's complement data
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// Write with two's complement data
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next_sample <= i_wb_data[15:0];
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next_sample <= i_wb_data[15:0];
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next_valid <= 1'b1;
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next_valid <= 1'b1;
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end else if (ztimer)
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end else if (ztimer)
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next_valid <= 1'b0;
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next_valid <= 1'b0;
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// The interrupt line will remain high until writing a new data value
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// The interrupt line will remain high until writing a new data value
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// clears it. This design does not permit turning off this interrupt.
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// clears it. This design does not permit turning off this interrupt.
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// If the interrupt needs to be turned off, then ignore it in the
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// If the interrupt needs to be turned off, then ignore it in the
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// interrupt controller.
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// interrupt controller.
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initial o_int = 1'b0;
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initial o_int = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_int <= (~next_valid);
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o_int <= (~next_valid);
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`ifdef USE_OSERDES
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// If we use an OSERDES on our final output, we should be able to
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// oversample by a factor of 4x (or perhaps more, but this works the
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// 4x number). Here is an example of figuring out what both of those
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// 4x oversamples are--first the primary, calculated as before, but then
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// also the alternate.
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reg [31:0] nco_phase, nco_phase_a, nco_phase_b, nco_phase_c,
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sample_step, tripl_step, tripl_nco_step;
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initial nco_base = 32'h00;
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always @(posedge i_clk)
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if (ztimer)
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sample_step <= nco_step
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+ { {(32-16-5){next_sample[15]}}, next_sample, 5'h00 };
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// Multiply by three ... never that easy
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always @(posedge i_clk)
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tripl_nco_step <= nco_step + { nco_step[30:0], 1'b0 };
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always @(posedge i_clk)
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if (ztimer)
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tripl_step <= tripl_nco_step
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+ { {(32-16-5){next_sample[15]}}, next_sample, 5'h00 };
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+ { {(32-16-6){next_sample[15]}}, next_sample, 6'h00 };
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wire [31:0] base_step;
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assign nco_base_step = sample_step;
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always @(posedge i_clk)
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nco_phase_a <= nco_phase + sample_step;
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always @(posedge i_clk)
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nco_phase_b <= nco_phase + { sample_step[30:0], 1'b0 };
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always @(posedge i_clk)
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nco_phase_c <= nco_phase + tripl_step;
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always @(posedge i_clk)
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nco_phase <= nco_phase + { sample_step[29:0], 2'b00 };
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// Output a two-bit waveform. Send each bit to GPIO port(s), with
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// roughly the same number of ports per bit.
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assign o_tx = { nco_phase_a[31:30], nco_base_b[31:30],
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nco_phase_c[31:30], nco_phase[31:30] };
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`else
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// Adjust the gain for a maximum frequency offset just greater than
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// Adjust the gain for a maximum frequency offset just greater than
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// 75 kHz. (We would've done 75kHz exactly, but it required a multiply
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// 75 kHz. (We would've done 75kHz exactly, but it required a multiply
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// and this doesn't.)
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// and this doesn't.)
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reg [31:0] nco_phase;
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initial nco_phase = 32'h00;
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initial nco_phase = 32'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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nco_phase <= nco_phase + nco_step
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nco_phase <= nco_phase + nco_step
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+ { {(32-16-7){sample_out[15]}}, sample_out, 7'h00 };
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+ { {(32-16-7){sample_out[15]}}, sample_out, 7'h00 };
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assign o_tx = nco_phase[31];
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assign o_tx = nco_phase[31];
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_wb_addr)
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if (i_wb_addr)
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o_wb_data <= nco_step;
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o_wb_data <= nco_step;
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else
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else
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o_wb_data <= { reload_value, sample_out[15:1], o_int };
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o_wb_data <= { reload_value, sample_out[15:1], o_int };
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initial o_wb_ack = 1'b0;
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initial o_wb_ack = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
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assign o_wb_stall = 1'b0;
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assign o_wb_stall = 1'b0;
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endmodule
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endmodule
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