| Line 6... |
Line 6... |
//
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//
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// Purpose: This file is a test bench wrapper around the wishbone scope,
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// Purpose: This file is a test bench wrapper around the wishbone scope,
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// designed to create a "signal" which can then be scoped and
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// designed to create a "signal" which can then be scoped and
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// proven. In our case here, the "signal" is a counter. When we test
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// proven. In our case here, the "signal" is a counter. When we test
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// the scope within our bench/cpp Verilator testbench, we'll know if our
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// the scope within our bench/cpp Verilator testbench, we'll know if our
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// test was "correct" if the counter 1) only ever counts by 1, and 2) if
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// test was "correct" if the counter 1) only ever increments by 1, and
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// the trigger lands on thte right data sample.
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// 2) if the trigger lands on thte right data sample.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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| Line 38... |
Line 38... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
|
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`default_nettype none
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//
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module wbscope_tb(i_clk,
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module wbscope_tb(i_clk,
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// i_rst is required by our test infrastructure, yet unused here
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// i_rst is required by our test infrastructure, yet unused here
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i_rst,
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i_rst,
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// The test data. o_data is internally generated here from a
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// The test data. o_data is internally generated here from a
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// counter, i_trigger is given externally
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// counter, i_trigger is given externally
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| Line 50... |
Line 52... |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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// wishbone bus outputs
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// wishbone bus outputs
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// And our output interrupt
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// And our output interrupt
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o_interrupt);
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o_interrupt);
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input i_clk, i_rst, i_trigger;
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input wire i_clk, i_rst, i_trigger;
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output wire [31:0] o_data;
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output wire [31:0] o_data;
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//
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//
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input wire i_wb_addr;
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input [31:0] i_wb_data;
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input wire [31:0] i_wb_data;
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//
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//
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output wire o_wb_ack;
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output wire o_wb_ack;
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output wire o_wb_stall;
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output wire o_wb_stall;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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//
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//
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output o_interrupt;
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output wire o_interrupt;
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|
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reg [30:0] counter;
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reg [30:0] counter;
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initial counter = 0;
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initial counter = 0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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counter <= counter + 1'b1;
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counter <= counter + 1'b1;
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