| Line 2... |
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//
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//
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// Filename: wbscope_tb.v
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// Filename: wbscope_tb.v
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//
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//
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// Project: WBScope, a wishbone hosted scope
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// Project: WBScope, a wishbone hosted scope
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//
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//
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// Purpose:
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// Purpose: This file is a test bench wrapper around the wishbone scope,
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// designed to create a "signal" which can then be scoped and
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// proven. In our case here, the "signal" is a counter. When we test
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// the scope within our bench/cpp Verilator testbench, we'll know if our
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// test was "correct" if the counter 1) only ever counts by 1, and 2) if
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// the trigger lands on thte right data sample.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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| Line 33... |
Line 38... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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module wbscope_tb(i_clk, i_rst, i_trigger, o_data,
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module wbscope_tb(i_clk,
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// i_rst is required by our test infrastructure, yet unused here
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i_rst,
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// The test data. o_data is internally generated here from a
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// counter, i_trigger is given externally
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i_trigger, o_data,
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// Wishbone bus interaction
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_data, o_interrupt);
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// wishbone bus outputs
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o_wb_ack, o_wb_stall, o_wb_data,
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// And our output interrupt
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o_interrupt);
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input i_clk, i_rst, i_trigger;
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input i_clk, i_rst, i_trigger;
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output wire [31:0] o_data;
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output wire [31:0] o_data;
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//
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//
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_addr;
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input i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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//
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//
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output wire o_wb_ack;
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output wire o_wb_ack;
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output wire o_wb_stall;
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output wire [31:0] o_wb_data;
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output wire [31:0] o_wb_data;
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//
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//
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output o_interrupt;
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output o_interrupt;
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reg [30:0] counter;
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reg [30:0] counter;
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| Line 57... |
Line 72... |
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assign o_data = { i_trigger, counter };
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assign o_data = { i_trigger, counter };
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wire wb_stall_ignored;
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wire wb_stall_ignored;
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wbscope #(5'd6, 32, 1)
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wbscope #(.LGMEM(5'd6), .BUSW(32), .SYNCHRONOUS(1),
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.DEFAULT_HOLDOFF(1))
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scope(i_clk, 1'b1, i_trigger, o_data,
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scope(i_clk, 1'b1, i_trigger, o_data,
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i_clk, i_wb_cyc, i_wb_stb, i_wb_we,
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i_clk, i_wb_cyc, i_wb_stb, i_wb_we,
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i_wb_addr, i_wb_data,
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i_wb_addr, i_wb_data,
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o_wb_ack, wb_stall_ignored, o_wb_data,
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o_wb_ack, wb_stall_ignored, o_wb_data,
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o_interrupt);
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o_interrupt);
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assign o_wb_stall = 1'b0;
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// verilator lint_off UNUSED
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wire [1:0] unused;
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assign unused = { i_rst, wb_stall_ignored };
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// verilator lint_on UNUSED
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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