| Line 84... |
Line 84... |
internal registers upon command, and to make many of those registers
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internal registers upon command, and to make many of those registers
|
available via the bus.
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available via the bus.
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|
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When I then needed to make the project run in real-time, as opposed to the
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When I then needed to make the project run in real-time, as opposed to the
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manually stepped approach, I generated a scope like this one. I had already
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manually stepped approach, I generated a scope like this one. I had already
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bench tested the components on the hardware itself. Thu, testing and
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bench tested the components on the hardware itself. Thus, testing and
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development continued on the hardware, and the scope helped me see what was
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development continued on the hardware, and the scope helped me see what was
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going right or wrong. The great advantage of the approach was that, at the
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going right or wrong. The great advantage of the approach was that, at the
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end of the project, I didn't need to do any hardware in the loop testing.
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end of the project, I didn't need to do any hardware in the loop testing.
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All of the testing that had been accomplished prior to that date was already
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All of the testing that had been accomplished prior to that date was already
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hardware in the loop testing.
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hardware in the loop testing.
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| Line 158... |
Line 158... |
Once the core has {\tt STOPPED}, the data within it may be read back off.
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Once the core has {\tt STOPPED}, the data within it may be read back off.
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\end{enumerate}
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\end{enumerate}
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Let's go through that list again. First, before using the scope, the holdoff
|
Let's go through that list again. First, before using the scope, the holdoff
|
needs to be set. The scope is designed so that setting the scope control value
|
needs to be set. The scope is designed so that setting the scope control value
|
to the holdoff alone will reset the scope from whatever condition it was in,
|
to the holdoff alone, with all other bits set to zero, will reset the scope
|
|
from whatever condition it was in,
|
freeing it to run. Once running, then upon every clock enabled clock, one
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freeing it to run. Once running, then upon every clock enabled clock, one
|
sample of data is read into the scope and recorded. Once every memory value
|
sample of data is read into the scope and recorded. Once every memory value
|
is filled, the scope has been {\tt PRIMED}. Once the scope has been
|
is filled, the scope has been {\tt PRIMED}. Once the scope has been
|
{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be
|
{\tt PRIMED}, it will then be responsive to its trigger. Should the trigger be
|
active on a clock--enabled input, the scope will then be {\tt TRIGGERED}. It
|
active on an input clock with the clock--enable line set, the scope will then
|
|
be {\tt TRIGGERED}. It
|
will then count for the number of clocks in the holdoff before stopping
|
will then count for the number of clocks in the holdoff before stopping
|
collection, placing it in the {\tt STOPPED} state. (Don't change the holdoff
|
collection, placing it in the {\tt STOPPED} state. \footnote{You can even
|
during between triggered and stopped, or it may stop at some other non--holdoff
|
change the holdoff while the scope is running by writing a new holdoff value
|
value!) If the holdoff is zero, the last sample in the buffer will be the
|
together with setting the {\tt RESET\_n} bit of the control register. However,
|
sample containing the trigger. Likewise if the holdoff is one less than the
|
if you do this after the core has triggered it may stop at some other
|
size of the memory, the first sample in the buffer will be the one containing
|
non--holdoff value!} If the holdoff is zero, the last sample in the buffer
|
the trigger.
|
will be the sample containing the trigger. Likewise if the holdoff is one
|
|
less than the size of the memory, the first sample in the buffer will be the
|
|
one containing the trigger.
|
|
|
There are two further commands that will affect the operation of the scope. The
|
There are two further commands that will affect the operation of the scope. The
|
first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing
|
first is the {\tt MANUAL} trigger command/bit. This bit may be set by writing
|
the holdoff to the control register while setting this bit high. This will
|
the holdoff to the control register while setting this bit high. This will
|
cause the scope to trigger immediately. If coupled with a {\tt RESET} command,
|
cause the scope to trigger as soon as it is primed. If the {\tt RESET\_n}
|
that is if the {\tt RESET\_n} bit isn't also set, then recording will start
|
bit is also set so as to prevent an internal reset, and if the scope was already
|
at the beginning and the scope will first wait until its {\tt PRIMED} state
|
primed, then manual trigger command will cause it to trigger immediately.
|
before the manual trigger takes effect.
|
|
|
|
The last command that can affect the operation of the scope is the {\tt DISABLE}
|
The last command that can affect the operation of the scope is the {\tt DISABLE}
|
command/bit in the control register. Setting this bit will prevent the scope
|
command/bit in the control register. Setting this bit will prevent the scope
|
from triggering, or if {\tt TRIGGERED}, it will prevent the scope from
|
from triggering, or if {\tt TRIGGERED}, it will prevent the scope from
|
generating an interrupt.
|
generating an interrupt.
|
| Line 190... |
Line 193... |
Finally, be careful how you set the clock enable line. If the clock enable
|
Finally, be careful how you set the clock enable line. If the clock enable
|
line leaves the clock too often disabled, the scope might never prime in any
|
line leaves the clock too often disabled, the scope might never prime in any
|
reasonable amount of time.
|
reasonable amount of time.
|
|
|
So, in summary, to use this scope you first set the holdoff value in the
|
So, in summary, to use this scope you first set the holdoff value in the
|
control register. Second, you wait until the scope has been {\tt TRIGGERED} and
|
control register. Second, you wait until the scope has been {\tt TRIGGERED}
|
stopped. Finally, you read from the data register once for every memory value
|
and {\tt STOPPED}. Finally, you read from the data register once for every
|
in the buffer and you can then sit back, relax, and study what took place
|
memory value in the buffer and you can then sit back, relax, and study what
|
within the FPGA.
|
took place within the FPGA. Additional modes allow you to manually trigger
|
|
the scope, or to disable the automatic trigger entirely.
|
|
|
\chapter{Registers}
|
\chapter{Registers}
|
|
|
This scope core supports two registers, as listed in
|
This scope core supports two registers, as listed in
|
Tbl.~\ref{tbl:reglist}: a control register and a data register.
|
Tbl.~\ref{tbl:reglist}: a control register and a data register.
|
| Line 330... |
Line 334... |
acts as a wishbone slave, and that all accesses to the wishbone scope
|
acts as a wishbone slave, and that all accesses to the wishbone scope
|
registers become 32--bit reads and writes to this interface. You may also wish
|
registers become 32--bit reads and writes to this interface. You may also wish
|
to note that the scope supports pipeline reads from the data port, to speed
|
to note that the scope supports pipeline reads from the data port, to speed
|
up reading the results out.
|
up reading the results out.
|
|
|
|
What this table doesn't show is that all accesses to the port take a single
|
|
clock. That is, if the {\tt i\_wb\_stb} line is high on one clock, the
|
|
{\tt i\_wb\_ack} line will be high the next. Further, the {\tt o\_wb\_stall}
|
|
line is tied to zero.
|
\chapter{IO Ports}
|
\chapter{IO Ports}
|
|
|
The ports are listed in Table.~\ref{tbl:ioports}.
|
The ports are listed in Table.~\ref{tbl:ioports}.
|
\begin{table}[htbp]
|
\begin{table}[htbp]
|
\begin{center}
|
\begin{center}
|
