| Line 66... |
Line 66... |
// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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| Line 185... |
Line 185... |
);
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);
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|
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// AXI4LITE signals
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// AXI4LITE signals
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
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reg axi_awready;
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reg axi_awready;
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reg axi_wready;
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// reg [1 : 0] axi_bresp;
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// reg [1 : 0] axi_bresp;
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reg axi_bvalid;
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reg axi_bvalid;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
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reg axi_arready;
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reg axi_arready;
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// reg [1 : 0] axi_rresp;
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// reg [1 : 0] axi_rresp;
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reg axi_rvalid;
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wire write_stb;
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wire write_stb;
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///////////////////////////////////////////////////
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///////////////////////////////////////////////////
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| Line 212... |
Line 210... |
// file.
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// file.
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//
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//
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// Gisselquist Technology, LLC, claims no copyright
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// Gisselquist Technology, LLC, claims no copyright
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// or ownership of this section of the code.
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// or ownership of this section of the code.
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//
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//
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wire i_reset;
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wire i_reset, axi_bstall, axi_rstall;
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assign i_reset = !S_AXI_ARESETN;
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assign i_reset = !S_AXI_ARESETN;
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|
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always @(posedge S_AXI_ACLK)
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always @(*)
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if (i_reset)
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if ((!axi_bstall)&&(S_AXI_AWVALID)&&(S_AXI_WVALID))
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axi_awready <= 1'b0;
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else if ((!axi_awready)&&(S_AXI_AWVALID)&&(S_AXI_WVALID))
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axi_awready <= 1'b1;
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axi_awready <= 1'b1;
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else
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else
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axi_awready <= 1'b0;
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axi_awready <= 1'b0;
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assign S_AXI_AWREADY = axi_awready;
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assign S_AXI_AWREADY = axi_awready;
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assign S_AXI_WREADY = axi_awready;
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always @(posedge S_AXI_ACLK)
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always @(posedge S_AXI_ACLK)
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if ((!axi_awready)&&(S_AXI_AWVALID)&&(S_AXI_WVALID))
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if ((S_AXI_AWVALID)&&(S_AXI_AWREADY))
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axi_awaddr <= S_AXI_AWADDR;
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axi_awaddr <= S_AXI_AWADDR;
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initial axi_bvalid = 0;
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always @(posedge S_AXI_ACLK)
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always @(posedge S_AXI_ACLK)
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if (i_reset)
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if (i_reset)
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axi_wready <= 1'b0;
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else if ((!axi_wready)&&(S_AXI_WVALID)&&(S_AXI_AWVALID))
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axi_wready <= 1'b1;
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else
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axi_wready <= 1'b0;
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assign S_AXI_WREADY = axi_wready;
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|
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always @(posedge S_AXI_ACLK)
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if (i_reset)
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begin
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axi_bvalid <= 0;
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axi_bvalid <= 0;
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// axi_bresp <= 2'b00;
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else if (write_stb)
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end else if ((~axi_bvalid)&&(write_stb))
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begin
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axi_bvalid <= 1'b1;
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axi_bvalid <= 1'b1;
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// axi_bresp <= 2'b00; // 'Okay' response
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else if (S_AXI_BREADY)
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end else if ((S_AXI_BREADY)&&(axi_bvalid))
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axi_bvalid <= 1'b0;
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axi_bvalid <= 1'b0;
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assign S_AXI_BRESP = 2'b00; // An 'OKAY' response
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assign S_AXI_BRESP = 2'b00; // An 'OKAY' response
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assign S_AXI_BVALID= axi_bvalid;
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assign S_AXI_BVALID= axi_bvalid;
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|
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assign axi_bstall = (S_AXI_BVALID)&&(!S_AXI_BREADY);
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|
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always @(*)
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if (i_reset)
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axi_arready = 1'b0;
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else if (axi_rstall)
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axi_arready = 1'b0;
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else
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axi_arready = 1'b1;
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|
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always @(posedge S_AXI_ACLK)
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always @(posedge S_AXI_ACLK)
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if (i_reset)
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if (i_reset)
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begin
|
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axi_arready <= 1'b0;
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axi_araddr <= 0;
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axi_araddr <= 0;
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end else if ((!axi_arready)&&(S_AXI_ARVALID))
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else if ((axi_arready)&&(S_AXI_ARVALID))
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begin
|
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axi_arready <= 1'b1;
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axi_araddr <= S_AXI_ARADDR;
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axi_araddr <= S_AXI_ARADDR;
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end else
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axi_arready <= 1'b0;
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assign S_AXI_ARREADY = axi_arready;
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assign S_AXI_ARREADY = axi_arready;
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|
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reg [1:0] rvalid;
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initial rvalid = 2'b00;
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always @(posedge S_AXI_ACLK)
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always @(posedge S_AXI_ACLK)
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if (i_reset)
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if (i_reset)
|
begin
|
rvalid <= 2'b00;
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axi_rvalid <= 0;
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else if ((axi_arready)&&(S_AXI_ARVALID))
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// axi_rresp <= 0;
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rvalid <= 2'b01;
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end else if ((axi_arready)&&(S_AXI_ARVALID)&&(!axi_rvalid))
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else if (rvalid == 2'b01)
|
begin
|
rvalid <= 2'b10;
|
axi_rvalid <= 1'b0;
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else if (S_AXI_RREADY)
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// axi_rresp <= 2'b00;
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rvalid <= 2'b00;
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end else if ((axi_rvalid)&&(S_AXI_RREADY))
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axi_rvalid <= 1'b0;
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assign S_AXI_RVALID = rvalid[1];
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assign S_AXI_RVALID = axi_rvalid;
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assign S_AXI_RRESP = 2'b00;
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assign S_AXI_RRESP = 2'b00;
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|
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assign axi_rstall = ((rvalid[0])||(S_AXI_RVALID)&&(!S_AXI_RREADY));
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///////////////////////////////////////////////////
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///////////////////////////////////////////////////
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//
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//
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| Line 312... |
Line 303... |
wire read_from_data;
|
wire read_from_data;
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assign read_from_data = (S_AXI_ARVALID)&&(S_AXI_ARREADY)
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assign read_from_data = (S_AXI_ARVALID)&&(S_AXI_ARREADY)
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&&(axi_araddr[0]);
|
&&(axi_araddr[0]);
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|
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assign write_stb = ((axi_awready)&&(S_AXI_AWVALID)
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assign write_stb = ((axi_awready)&&(S_AXI_AWVALID)
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&&(axi_wready)&&(S_AXI_WVALID));
|
&&(S_AXI_WVALID));
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wire write_to_control;
|
wire write_to_control;
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assign write_to_control = (write_stb)&&(!axi_awaddr[0]);
|
assign write_to_control = (write_stb)&&(!axi_awaddr[0]);
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|
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reg read_address;
|
reg read_address;
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always @(posedge bus_clock)
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always @(posedge bus_clock)
|
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if ((axi_arready)&&(S_AXI_ARVALID))
|
read_address <= axi_araddr[0];
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read_address <= axi_araddr[0];
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|
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wire [31:0] i_wb_data;
|
wire [31:0] i_wb_data;
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assign i_wb_data = S_AXI_WDATA;
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assign i_wb_data = S_AXI_WDATA;
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|
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| Line 377... |
Line 369... |
(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
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(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
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reg [2:0] r_iflags;
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reg [2:0] r_iflags;
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|
|
// Resets are synchronous to the bus clock, not the data clock
|
// Resets are synchronous to the bus clock, not the data clock
|
// so do a clock transfer here
|
// so do a clock transfer here
|
initial q_iflags = 3'b000;
|
initial { q_iflags, r_iflags } = 6'h0;
|
initial r_reset_complete = 1'b0;
|
initial r_reset_complete = 1'b0;
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always @(posedge i_data_clk)
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always @(posedge i_data_clk)
|
begin
|
begin
|
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
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q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
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r_iflags <= q_iflags;
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r_iflags <= q_iflags;
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| Line 403... |
Line 395... |
q_reset_complete <= r_reset_complete;
|
q_reset_complete <= r_reset_complete;
|
qq_reset_complete <= q_reset_complete;
|
qq_reset_complete <= q_reset_complete;
|
end
|
end
|
|
|
assign bw_reset_complete = qq_reset_complete;
|
assign bw_reset_complete = qq_reset_complete;
|
|
|
|
`ifdef FORMAL
|
|
always @($global_clock)
|
|
if (f_past_valid_data)
|
|
begin
|
|
if ($rose(r_reset_complete))
|
|
assert(bw_reset_request);
|
|
end
|
|
`endif
|
end endgenerate
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end endgenerate
|
|
|
//
|
//
|
// Set up the trigger
|
// Set up the trigger
|
//
|
//
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| Line 437... |
Line 438... |
initial counter = 0;
|
initial counter = 0;
|
always @(posedge i_data_clk)
|
always @(posedge i_data_clk)
|
if (dw_reset)
|
if (dw_reset)
|
counter <= 0;
|
counter <= 0;
|
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
|
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
|
begin
|
|
counter <= counter + 1'b1;
|
counter <= counter + 1'b1;
|
end
|
|
always @(posedge i_data_clk)
|
always @(posedge i_data_clk)
|
if ((!dr_triggered)||(dw_reset))
|
if ((!dr_triggered)||(dw_reset))
|
dr_stopped <= 1'b0;
|
dr_stopped <= 1'b0;
|
else if (HOLDOFFBITS > 1) // if (i_ce)
|
else if (HOLDOFFBITS > 1) // if (i_ce)
|
dr_stopped <= (counter >= br_holdoff);
|
dr_stopped <= (counter >= br_holdoff);
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| Line 549... |
Line 549... |
assign bw_triggered = r_oflags[1];
|
assign bw_triggered = r_oflags[1];
|
assign bw_primed = r_oflags[0];
|
assign bw_primed = r_oflags[0];
|
end endgenerate
|
end endgenerate
|
|
|
// Reads use the bus clock
|
// Reads use the bus clock
|
|
initial raddr = 0;
|
always @(posedge bus_clock)
|
always @(posedge bus_clock)
|
begin
|
begin
|
if ((bw_reset_request)||(write_to_control))
|
if ((bw_reset_request)||(write_to_control))
|
raddr <= 0;
|
raddr <= 0;
|
else if ((read_from_data)&&(bw_stopped))
|
else if ((read_from_data)&&(bw_stopped))
|
raddr <= raddr + 1'b1; // Data read, when stopped
|
raddr <= raddr + 1'b1; // Data read, when stopped
|
end
|
end
|
|
|
reg [(LGMEM-1):0] this_addr;
|
reg [(LGMEM-1):0] this_addr;
|
always @(posedge bus_clock)
|
always @(posedge bus_clock)
|
if (read_from_data)
|
if ((bw_stopped)&&(read_from_data))
|
this_addr <= raddr + waddr + 1'b1;
|
this_addr <= raddr + waddr + 1'b1;
|
else
|
else
|
this_addr <= raddr + waddr;
|
this_addr <= raddr + waddr;
|
|
|
reg [31:0] nxt_mem;
|
reg [31:0] nxt_mem;
|
always @(posedge bus_clock)
|
always @(posedge bus_clock)
|
|
if (read_from_data)
|
nxt_mem <= mem[this_addr];
|
nxt_mem <= mem[this_addr];
|
|
|
wire [19:0] full_holdoff;
|
wire [19:0] full_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
generate if (HOLDOFFBITS < 20)
|
generate if (HOLDOFFBITS < 20)
|
| Line 578... |
Line 580... |
|
|
reg [31:0] o_bus_data;
|
reg [31:0] o_bus_data;
|
wire [4:0] bw_lgmem;
|
wire [4:0] bw_lgmem;
|
assign bw_lgmem = LGMEM;
|
assign bw_lgmem = LGMEM;
|
always @(posedge bus_clock)
|
always @(posedge bus_clock)
|
|
if (rvalid[0])
|
|
begin
|
if (!read_address) // Control register read
|
if (!read_address) // Control register read
|
o_bus_data <= { bw_reset_request,
|
o_bus_data <= { bw_reset_request,
|
bw_stopped,
|
bw_stopped,
|
bw_triggered,
|
bw_triggered,
|
bw_primed,
|
bw_primed,
|
| Line 592... |
Line 596... |
full_holdoff };
|
full_holdoff };
|
else if (!bw_stopped) // read, prior to stopping
|
else if (!bw_stopped) // read, prior to stopping
|
o_bus_data <= i_data;
|
o_bus_data <= i_data;
|
else // if (i_wb_addr) // Read from FIFO memory
|
else // if (i_wb_addr) // Read from FIFO memory
|
o_bus_data <= nxt_mem; // mem[raddr+waddr];
|
o_bus_data <= nxt_mem; // mem[raddr+waddr];
|
|
end
|
|
|
assign S_AXI_RDATA = o_bus_data;
|
assign S_AXI_RDATA = o_bus_data;
|
|
|
reg br_level_interrupt;
|
reg br_level_interrupt;
|
initial br_level_interrupt = 1'b0;
|
initial br_level_interrupt = 1'b0;
|
| Line 612... |
Line 617... |
wire [44:0] unused;
|
wire [44:0] unused;
|
assign unused = { S_AXI_WSTRB, S_AXI_ARPROT, S_AXI_AWPROT,
|
assign unused = { S_AXI_WSTRB, S_AXI_ARPROT, S_AXI_AWPROT,
|
axi_awaddr[3:1], axi_araddr[3:1],
|
axi_awaddr[3:1], axi_araddr[3:1],
|
i_wb_data[30:28], i_wb_data[25:0] };
|
i_wb_data[30:28], i_wb_data[25:0] };
|
// verilator lint_on UNUSED
|
// verilator lint_on UNUSED
|
|
`ifdef FORMAL
|
|
generate if (SYNCHRONOUS)
|
|
begin
|
|
|
|
always @(*)
|
|
assume(i_data_clk == S_AXI_ACLK);
|
|
|
|
end else begin
|
|
localparam CKSTEP_BITS = 3;
|
|
localparam [CKSTEP_BITS-1:0]
|
|
MAX_STEP = { 1'b0, {(CKSTEP_BITS-1){1'b1}} };
|
|
|
|
// "artificially" generate two clocks
|
|
`ifdef VERIFIC
|
|
(* gclk *) wire gbl_clock;
|
|
global clocking @(posedge gbl_clock); endclocking
|
|
`endif
|
|
|
|
(* anyconst *) wire [CKSTEP_BITS-1:0] f_data_step, f_bus_step;
|
|
reg [CKSTEP_BITS-1:0] f_data_count, f_bus_count;
|
|
|
|
always @(*)
|
|
begin
|
|
assume(f_data_step > 0);
|
|
assume(f_bus_step > 0);
|
|
assume(f_data_step <= MAX_STEP);
|
|
assume(f_bus_step <= MAX_STEP);
|
|
|
|
assume((f_data_step == MAX_STEP)
|
|
||(f_bus_step == MAX_STEP));
|
|
end
|
|
|
|
always @($global_clock)
|
|
begin
|
|
f_data_count <= f_data_count + f_data_step;
|
|
f_bus_count <= f_bus_count + f_bus_step;
|
|
|
|
assume(i_data_clk == f_data_count[CKSTEP_BITS-1]);
|
|
assume(bus_clock == f_bus_count[CKSTEP_BITS-1]);
|
|
end
|
|
|
|
always @($global_clock)
|
|
if (!$rose(i_data_clk))
|
|
begin
|
|
assume($stable(i_trigger));
|
|
assume($stable(i_data));
|
|
end
|
|
|
|
always @($global_clock)
|
|
if (!$rose(S_AXI_ACLK))
|
|
begin
|
|
assume($stable(S_AXI_ARESETN));
|
|
//
|
|
assume($stable(S_AXI_AWADDR));
|
|
assume($stable(S_AXI_AWPROT));
|
|
assume($stable(S_AXI_AWVALID));
|
|
//
|
|
assume($stable(S_AXI_WDATA));
|
|
assume($stable(S_AXI_WSTRB));
|
|
assume($stable(S_AXI_WVALID));
|
|
//
|
|
assume($stable(S_AXI_BREADY));
|
|
//
|
|
assume($stable(S_AXI_ARADDR));
|
|
assume($stable(S_AXI_ARPROT));
|
|
assume($stable(S_AXI_ARVALID));
|
|
//
|
|
assume($stable(S_AXI_RREADY));
|
|
//
|
|
end
|
|
|
|
end endgenerate
|
|
|
|
reg f_past_valid_bus, f_past_valid_gbl, f_past_valid_data;
|
|
initial { f_past_valid_bus, f_past_valid_gbl, f_past_valid_data }= 3'b0;
|
|
always @(posedge S_AXI_ACLK)
|
|
f_past_valid_bus = 1'b1;
|
|
|
|
generate if (!SYNCHRONOUS)
|
|
begin
|
|
always @($global_clock)
|
|
f_past_valid_gbl <= 1'b1;
|
|
|
|
always @(posedge i_data_clk)
|
|
f_past_valid_data = 1'b1;
|
|
|
|
always @(posedge i_data_clk)
|
|
if (f_past_valid_data)
|
|
assert($stable(o_interrupt));
|
|
|
|
always @($global_clock)
|
|
if ((f_past_valid_gbl)&&(!$rose(S_AXI_ACLK)))
|
|
begin
|
|
assert($stable(S_AXI_AWREADY));
|
|
assert($stable(S_AXI_ARREADY));
|
|
assert($stable(S_AXI_RDATA));
|
|
assert($stable(S_AXI_RRESP));
|
|
assert($stable(S_AXI_RVALID));
|
|
assert($stable(S_AXI_WREADY));
|
|
assert($stable(S_AXI_BRESP));
|
|
assert($stable(S_AXI_BVALID));
|
|
end
|
|
|
|
end else begin
|
|
|
|
always @(*)
|
|
f_past_valid_data = f_past_valid_bus;
|
|
always @(*)
|
|
f_past_valid_gbl = f_past_valid_bus;
|
|
|
|
end endgenerate
|
|
|
|
localparam F_LGDEPTH = 5;
|
|
wire [F_LGDEPTH-1:0] f_axi_rd_outstanding,
|
|
f_axi_wr_outstanding,
|
|
f_axi_awr_outstanding;
|
|
|
|
faxil_slave #(
|
|
// .C_S_AXI_DATA_WIDth(C_S_AXI_DATA_WIDTH),
|
|
// Width of S_AXI address bus
|
|
.C_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
|
|
.F_LGDEPTH(F_LGDEPTH),
|
|
.F_OPT_HAS_CACHE(1'b0),
|
|
// .F_OPT_CLK2FFLOGIC(!SYNCHRONOUS),
|
|
.F_AXI_MAXWAIT(5'h6),
|
|
.F_AXI_MAXDELAY(5'h6),
|
|
) faxil_slave(
|
|
.i_clk(S_AXI_ACLK),
|
|
.i_axi_reset_n(S_AXI_ARESETN),
|
|
//
|
|
.i_axi_awaddr(S_AXI_AWADDR),
|
|
.i_axi_awprot(S_AXI_AWPROT),
|
|
.i_axi_awcache(4'h0),
|
|
.i_axi_awvalid(S_AXI_AWVALID),
|
|
.i_axi_awready(S_AXI_AWREADY),
|
|
//
|
|
.i_axi_wdata(S_AXI_WDATA),
|
|
.i_axi_wstrb(S_AXI_WSTRB),
|
|
.i_axi_wvalid(S_AXI_WVALID),
|
|
.i_axi_wready(S_AXI_WREADY),
|
|
//
|
|
.i_axi_bresp(S_AXI_BRESP),
|
|
.i_axi_bvalid(S_AXI_BVALID),
|
|
.i_axi_bready(S_AXI_BREADY),
|
|
//
|
|
.i_axi_araddr(S_AXI_ARADDR),
|
|
.i_axi_arprot(S_AXI_ARPROT),
|
|
.i_axi_arvalid(S_AXI_ARVALID),
|
|
.i_axi_arready(S_AXI_ARREADY),
|
|
.i_axi_arcache(4'h0),
|
|
//
|
|
.i_axi_rdata(S_AXI_RDATA),
|
|
.i_axi_rresp(S_AXI_RRESP),
|
|
.i_axi_rvalid(S_AXI_RVALID),
|
|
.i_axi_rready(S_AXI_RREADY),
|
|
//
|
|
.f_axi_rd_outstanding(f_axi_rd_outstanding),
|
|
.f_axi_wr_outstanding(f_axi_wr_outstanding),
|
|
.f_axi_awr_outstanding(f_axi_awr_outstanding));
|
|
|
|
always @(*)
|
|
begin
|
|
assert(f_axi_wr_outstanding == f_axi_awr_outstanding);
|
|
if (axi_bvalid)
|
|
assert(f_axi_wr_outstanding == 1);
|
|
else
|
|
assert(f_axi_wr_outstanding == 0);
|
|
if (|rvalid)
|
|
assert(f_axi_rd_outstanding == 1);
|
|
else
|
|
assert(f_axi_rd_outstanding == 0);
|
|
assert(rvalid != 2'b11);
|
|
end
|
|
|
|
always @(*)
|
|
if (dr_triggered)
|
|
assert(dr_primed);
|
|
|
|
always @(*)
|
|
if (dr_stopped)
|
|
assert((dr_primed)&&(dr_triggered));
|
|
|
|
reg dr_triggered, dr_primed;
|
|
wire dw_trigger;
|
|
assign dw_trigger = (dr_primed)&&(
|
|
((i_trigger)&&(!dw_disable_trigger))
|
|
||(dw_manual_trigger));
|
|
|
|
(* anyconst *) wire [(LGMEM-1):0] f_addr;
|
|
reg [31:0] f_data;
|
|
reg f_filled;
|
|
|
|
initial f_filled = 1'b0;
|
|
always @(posedge i_data_clk)
|
|
if (dw_reset)
|
|
f_filled <= 1'b0;
|
|
else if ((i_ce)&&(!dr_stopped)&&(waddr == f_addr))
|
|
f_filled <= 1'b1;
|
|
|
|
always @(posedge i_data_clk)
|
|
if (waddr > f_addr)
|
|
assert(f_filled);
|
|
|
|
always @(posedge i_data_clk)
|
|
if (!f_filled)
|
|
assert(!dr_primed);
|
|
|
|
always @(posedge i_data_clk)
|
|
if ((i_ce)&&(!dr_stopped)&&(waddr == f_addr))
|
|
f_data <= wr_piped_data;
|
|
|
|
always @(posedge i_data_clk)
|
|
if (f_filled)
|
|
assert(mem[f_addr] == f_data);
|
|
|
|
`endif
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
