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https://opencores.org/ocsvn/wbscope/wbscope/trunk
[/] [wbscope/] [trunk/] [rtl/] [wbscope.v] - Diff between revs 13 and 14
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| Rev 13 |
Rev 14 |
| Line 264... |
Line 264... |
end else if ((i_ce)&&(!dr_stopped))
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end else if ((i_ce)&&(!dr_stopped))
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begin
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begin
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// mem[waddr] <= i_data;
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// mem[waddr] <= i_data;
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waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
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waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
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if (!dr_primed)
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if (!dr_primed)
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begin
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//if (br_holdoff[(HOLDOFFBITS-1):LGMEM]==0)
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// dr_primed <= (waddr >= br_holdoff[(LGMEM-1):0]);
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// else
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dr_primed <= (&waddr);
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dr_primed <= (&waddr);
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end
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end
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end
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// Delay the incoming data so that we can get our trigger
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// Delay the incoming data so that we can get our trigger
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// logic to line up with the data. The goal is to have a
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// logic to line up with the data. The goal is to have a
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// hold off of zero place the trigger in the last memory
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// hold off of zero place the trigger in the last memory
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// address.
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// address.
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