| Line 25... |
Line 25... |
// The scope registers that it has stopped recording by
|
// The scope registers that it has stopped recording by
|
// setting the 'o_stopped' output flag.
|
// setting the 'o_stopped' output flag.
|
// 5. The scope recording is then paused until the next reset.
|
// 5. The scope recording is then paused until the next reset.
|
// 6. While stopped, the CPU can read the data from the scope
|
// 6. While stopped, the CPU can read the data from the scope
|
// 7. -- oldest to most recent
|
// 7. -- oldest to most recent
|
// 8. -- one value per i_rd&i_clk
|
// 8. -- one value per i_rd&i_data_clk
|
// 9. Writes to the data register reset the address to the
|
// 9. Writes to the data register reset the address to the
|
// beginning of the buffer
|
// beginning of the buffer
|
//
|
//
|
// Although the data width DW is parameterized, it is not very changable,
|
// Although the data width DW is parameterized, it is not very changable,
|
// since the width is tied to the width of the data bus, as is the
|
// since the width is tied to the width of the data bus, as is the
|
| Line 81... |
Line 81... |
//
|
//
|
//
|
//
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
//
|
//
|
//
|
//
|
module wbscope(i_clk, i_ce, i_trigger, i_data,
|
`default_nettype none
|
|
//
|
|
module wbscope(i_data_clk, i_ce, i_trigger, i_data,
|
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_wb_ack, o_wb_stall, o_wb_data,
|
o_interrupt);
|
o_interrupt);
|
parameter [4:0] LGMEM = 5'd10;
|
parameter [4:0] LGMEM = 5'd10;
|
parameter BUSW = 32;
|
parameter BUSW = 32;
|
parameter [0:0] SYNCHRONOUS=1;
|
parameter [0:0] SYNCHRONOUS=1;
|
parameter HOLDOFFBITS = 20;
|
parameter HOLDOFFBITS = 20;
|
parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
|
parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
|
// The input signals that we wish to record
|
// The input signals that we wish to record
|
input i_clk, i_ce, i_trigger;
|
input wire i_data_clk, i_ce, i_trigger;
|
input [(BUSW-1):0] i_data;
|
input wire [(BUSW-1):0] i_data;
|
// The WISHBONE bus for reading and configuring this scope
|
// The WISHBONE bus for reading and configuring this scope
|
input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
|
input wire i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
|
input i_wb_addr; // One address line only
|
input wire i_wb_addr; // One address line only
|
input [(BUSW-1):0] i_wb_data;
|
input wire [(BUSW-1):0] i_wb_data;
|
output wire o_wb_ack, o_wb_stall;
|
output wire o_wb_ack, o_wb_stall;
|
output reg [(BUSW-1):0] o_wb_data;
|
output wire [(BUSW-1):0] o_wb_data;
|
// And, finally, for a final flair --- offer to interrupt the CPU after
|
// And, finally, for a final flair --- offer to interrupt the CPU after
|
// our trigger has gone off. This line is equivalent to the scope
|
// our trigger has gone off. This line is equivalent to the scope
|
// being stopped. It is not maskable here.
|
// being stopped. It is not maskable here.
|
output wire o_interrupt;
|
output wire o_interrupt;
|
|
|
|
wire bus_clock;
|
|
assign bus_clock = i_wb_clk;
|
|
|
|
///////////////////////////////////////////////////
|
|
//
|
|
// Decode and handle the WB bus signaling in a
|
|
// (somewhat) portable manner
|
|
//
|
|
///////////////////////////////////////////////////
|
|
//
|
|
//
|
|
assign o_wb_stall = 1'b0;
|
|
|
|
wire read_from_data;
|
|
assign read_from_data = (i_wb_stb)&&(!i_wb_we)&&(i_wb_addr);
|
|
|
|
wire write_stb;
|
|
assign write_stb = (i_wb_stb)&&(i_wb_we);
|
|
|
|
wire write_to_control;
|
|
assign write_to_control = (write_stb)&&(!i_wb_addr);
|
|
|
|
reg read_address;
|
|
always @(posedge bus_clock)
|
|
read_address <= i_wb_addr;
|
|
|
reg [(LGMEM-1):0] raddr;
|
reg [(LGMEM-1):0] raddr;
|
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
|
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
|
|
|
// Our status/config register
|
// Our status/config register
|
wire bw_reset_request, bw_manual_trigger,
|
wire bw_reset_request, bw_manual_trigger,
|
bw_disable_trigger, bw_reset_complete;
|
bw_disable_trigger, bw_reset_complete;
|
reg [2:0] br_config;
|
reg [2:0] br_config;
|
reg [(HOLDOFFBITS-1):0] br_holdoff;
|
reg [(HOLDOFFBITS-1):0] br_holdoff;
|
initial br_config = 3'b0;
|
initial br_config = 3'b0;
|
initial br_holdoff = DEFAULT_HOLDOFF;
|
initial br_holdoff = DEFAULT_HOLDOFF;
|
always @(posedge i_wb_clk)
|
always @(posedge bus_clock)
|
if ((i_wb_stb)&&(!i_wb_addr))
|
if (write_to_control)
|
begin
|
|
if (i_wb_we)
|
|
begin
|
begin
|
br_config <= { i_wb_data[31],
|
br_config <= { i_wb_data[31],
|
i_wb_data[27],
|
i_wb_data[27],
|
i_wb_data[26] };
|
i_wb_data[26] };
|
br_holdoff = i_wb_data[(HOLDOFFBITS-1):0];
|
br_holdoff <= i_wb_data[(HOLDOFFBITS-1):0];
|
end
|
|
end else if (bw_reset_complete)
|
end else if (bw_reset_complete)
|
br_config[2] <= 1'b1;
|
br_config[2] <= 1'b1;
|
assign bw_reset_request = (!br_config[2]);
|
assign bw_reset_request = (!br_config[2]);
|
assign bw_manual_trigger = (br_config[1]);
|
assign bw_manual_trigger = (br_config[1]);
|
assign bw_disable_trigger = (br_config[0]);
|
assign bw_disable_trigger = (br_config[0]);
|
| Line 147... |
Line 172... |
|
|
// Resets are synchronous to the bus clock, not the data clock
|
// Resets are synchronous to the bus clock, not the data clock
|
// so do a clock transfer here
|
// so do a clock transfer here
|
initial q_iflags = 3'b000;
|
initial q_iflags = 3'b000;
|
initial r_reset_complete = 1'b0;
|
initial r_reset_complete = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_data_clk)
|
begin
|
begin
|
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
|
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
|
r_iflags <= q_iflags;
|
r_iflags <= q_iflags;
|
r_reset_complete <= (dw_reset);
|
r_reset_complete <= (dw_reset);
|
end
|
end
|
| Line 164... |
Line 189... |
reg qq_reset_complete;
|
reg qq_reset_complete;
|
// Pass an acknowledgement back from the data clock to the bus
|
// Pass an acknowledgement back from the data clock to the bus
|
// clock that the reset has been accomplished
|
// clock that the reset has been accomplished
|
initial q_reset_complete = 1'b0;
|
initial q_reset_complete = 1'b0;
|
initial qq_reset_complete = 1'b0;
|
initial qq_reset_complete = 1'b0;
|
always @(posedge i_wb_clk)
|
always @(posedge bus_clock)
|
begin
|
begin
|
q_reset_complete <= r_reset_complete;
|
q_reset_complete <= r_reset_complete;
|
qq_reset_complete <= q_reset_complete;
|
qq_reset_complete <= q_reset_complete;
|
end
|
end
|
|
|
| Line 178... |
Line 203... |
//
|
//
|
// Set up the trigger
|
// Set up the trigger
|
//
|
//
|
//
|
//
|
// Write with the i-clk, or input clock. All outputs read with the
|
// Write with the i-clk, or input clock. All outputs read with the
|
// WISHBONE-clk, or i_wb_clk clock.
|
// bus clock, or bus_clock as we've called it here.
|
reg dr_triggered, dr_primed;
|
reg dr_triggered, dr_primed;
|
wire dw_trigger;
|
wire dw_trigger;
|
assign dw_trigger = (dr_primed)&&(
|
assign dw_trigger = (dr_primed)&&(
|
((i_trigger)&&(!dw_disable_trigger))
|
((i_trigger)&&(!dw_disable_trigger))
|
||(dw_manual_trigger));
|
||(dw_manual_trigger));
|
initial dr_triggered = 1'b0;
|
initial dr_triggered = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_data_clk)
|
if (dw_reset)
|
if (dw_reset)
|
dr_triggered <= 1'b0;
|
dr_triggered <= 1'b0;
|
else if ((i_ce)&&(dw_trigger))
|
else if ((i_ce)&&(dw_trigger))
|
dr_triggered <= 1'b1;
|
dr_triggered <= 1'b1;
|
|
|
| Line 201... |
Line 226... |
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
|
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
|
|
|
reg dr_stopped;
|
reg dr_stopped;
|
initial dr_stopped = 1'b0;
|
initial dr_stopped = 1'b0;
|
initial counter = 0;
|
initial counter = 0;
|
always @(posedge i_clk)
|
always @(posedge i_data_clk)
|
if (dw_reset)
|
if (dw_reset)
|
counter <= 0;
|
counter <= 0;
|
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
|
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
begin
|
// 20 bits. Else we'd need to add a bit to comparison
|
|
// here.
|
|
counter <= counter + 1'b1;
|
counter <= counter + 1'b1;
|
end
|
end
|
always @(posedge i_clk)
|
always @(posedge i_data_clk)
|
if ((!dr_triggered)||(dw_reset))
|
if ((!dr_triggered)||(dw_reset))
|
dr_stopped <= 1'b0;
|
dr_stopped <= 1'b0;
|
else
|
else if (HOLDOFFBITS > 1) // if (i_ce)
|
dr_stopped <= (counter >= br_holdoff);
|
dr_stopped <= (counter >= br_holdoff);
|
|
else if (HOLDOFFBITS <= 1)
|
|
dr_stopped <= ((i_ce)&&(dw_trigger));
|
|
|
//
|
//
|
// Actually do our writes to memory. Record, via 'primed' when
|
// Actually do our writes to memory. Record, via 'primed' when
|
// the memory is full.
|
// the memory is full.
|
//
|
//
|
| Line 229... |
Line 254... |
// transfer for these signals.
|
// transfer for these signals.
|
//
|
//
|
reg [(LGMEM-1):0] waddr;
|
reg [(LGMEM-1):0] waddr;
|
initial waddr = {(LGMEM){1'b0}};
|
initial waddr = {(LGMEM){1'b0}};
|
initial dr_primed = 1'b0;
|
initial dr_primed = 1'b0;
|
always @(posedge i_clk)
|
always @(posedge i_data_clk)
|
if (dw_reset) // For simulation purposes, supply a valid value
|
if (dw_reset) // For simulation purposes, supply a valid value
|
begin
|
begin
|
waddr <= 0; // upon reset.
|
waddr <= 0; // upon reset.
|
dr_primed <= 1'b0;
|
dr_primed <= 1'b0;
|
end else if ((i_ce)&&(!dr_stopped))
|
end else if ((i_ce)&&(!dr_stopped))
|
begin
|
begin
|
// mem[waddr] <= i_data;
|
// mem[waddr] <= i_data;
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
|
dr_primed <= (dr_primed)||(&waddr);
|
if (!dr_primed)
|
|
begin
|
|
//if (br_holdoff[(HOLDOFFBITS-1):LGMEM]==0)
|
|
// dr_primed <= (waddr >= br_holdoff[(LGMEM-1):0]);
|
|
// else
|
|
|
|
dr_primed <= (&waddr);
|
|
end
|
end
|
end
|
always @(posedge i_clk)
|
|
|
// Delay the incoming data so that we can get our trigger
|
|
// logic to line up with the data. The goal is to have a
|
|
// hold off of zero place the trigger in the last memory
|
|
// address.
|
|
localparam STOPDELAY = 1;
|
|
wire [(BUSW-1):0] wr_piped_data;
|
|
generate
|
|
if (STOPDELAY == 0)
|
|
// No delay ... just assign the wires to our input lines
|
|
assign wr_piped_data = i_data;
|
|
else if (STOPDELAY == 1)
|
|
begin
|
|
//
|
|
// Delay by one means just register this once
|
|
reg [(BUSW-1):0] data_pipe;
|
|
always @(posedge i_data_clk)
|
|
if (i_ce)
|
|
data_pipe <= i_data;
|
|
assign wr_piped_data = data_pipe;
|
|
end else begin
|
|
// Arbitrary delay ... use a longer pipe
|
|
reg [(STOPDELAY*BUSW-1):0] data_pipe;
|
|
|
|
always @(posedge i_data_clk)
|
|
if (i_ce)
|
|
data_pipe <= { data_pipe[((STOPDELAY-1)*BUSW-1):0], i_data };
|
|
assign wr_piped_data = { data_pipe[(STOPDELAY*BUSW-1):((STOPDELAY-1)*BUSW)] };
|
|
end endgenerate
|
|
|
|
always @(posedge i_data_clk)
|
if ((i_ce)&&(!dr_stopped))
|
if ((i_ce)&&(!dr_stopped))
|
mem[waddr] <= i_data;
|
mem[waddr] <= wr_piped_data;
|
|
|
//
|
//
|
// Clock transfer of the status signals
|
// Clock transfer of the status signals
|
//
|
//
|
wire bw_stopped, bw_triggered, bw_primed;
|
wire bw_stopped, bw_triggered, bw_primed;
|
| Line 264... |
Line 326... |
//
|
//
|
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
|
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
|
reg [2:0] r_oflags;
|
reg [2:0] r_oflags;
|
initial q_oflags = 3'h0;
|
initial q_oflags = 3'h0;
|
initial r_oflags = 3'h0;
|
initial r_oflags = 3'h0;
|
always @(posedge i_wb_clk)
|
always @(posedge bus_clock)
|
if (bw_reset_request)
|
if (bw_reset_request)
|
begin
|
begin
|
q_oflags <= 3'h0;
|
q_oflags <= 3'h0;
|
r_oflags <= 3'h0;
|
r_oflags <= 3'h0;
|
end else begin
|
end else begin
|
| Line 280... |
Line 342... |
assign bw_triggered = r_oflags[1];
|
assign bw_triggered = r_oflags[1];
|
assign bw_primed = r_oflags[0];
|
assign bw_primed = r_oflags[0];
|
end endgenerate
|
end endgenerate
|
|
|
// Reads use the bus clock
|
// Reads use the bus clock
|
reg br_wb_ack;
|
reg br_wb_ack, br_pre_wb_ack;
|
initial br_wb_ack = 1'b0;
|
initial br_wb_ack = 1'b0;
|
wire bw_cyc_stb;
|
wire bw_cyc_stb;
|
assign bw_cyc_stb = (i_wb_stb);
|
assign bw_cyc_stb = (i_wb_stb);
|
always @(posedge i_wb_clk)
|
initial br_pre_wb_ack = 1'b0;
|
|
initial br_wb_ack = 1'b0;
|
|
always @(posedge bus_clock)
|
begin
|
begin
|
if ((bw_reset_request)
|
if ((bw_reset_request)||(write_to_control))
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
|
raddr <= 0;
|
raddr <= 0;
|
else if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)&&(bw_stopped))
|
else if ((read_from_data)&&(bw_stopped))
|
raddr <= raddr + 1'b1; // Data read, when stopped
|
raddr <= raddr + 1'b1; // Data read, when stopped
|
|
|
if ((bw_cyc_stb)&&(!i_wb_we))
|
br_pre_wb_ack <= bw_cyc_stb;
|
begin // Read from the bus
|
br_wb_ack <= (br_pre_wb_ack)&&(i_wb_cyc);
|
br_wb_ack <= 1'b1;
|
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
|
// We did this write above
|
|
br_wb_ack <= 1'b1;
|
|
else // Do nothing if either i_wb_cyc or i_wb_stb are low
|
|
br_wb_ack <= 1'b0;
|
|
end
|
end
|
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
|
|
|
reg [(LGMEM-1):0] this_addr;
|
|
always @(posedge bus_clock)
|
|
if (read_from_data)
|
|
this_addr <= raddr + waddr + 1'b1;
|
|
else
|
|
this_addr <= raddr + waddr;
|
|
|
reg [31:0] nxt_mem;
|
reg [31:0] nxt_mem;
|
always @(posedge i_wb_clk)
|
always @(posedge bus_clock)
|
nxt_mem <= mem[raddr+waddr+
|
nxt_mem <= mem[this_addr];
|
(((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)) ?
|
|
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
|
|
|
|
wire [19:0] full_holdoff;
|
wire [19:0] full_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
|
generate if (HOLDOFFBITS < 20)
|
generate if (HOLDOFFBITS < 20)
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
|
endgenerate
|
endgenerate
|
|
|
|
reg [31:0] o_bus_data;
|
wire [4:0] bw_lgmem;
|
wire [4:0] bw_lgmem;
|
assign bw_lgmem = LGMEM;
|
assign bw_lgmem = LGMEM;
|
always @(posedge i_wb_clk)
|
always @(posedge bus_clock)
|
if (!i_wb_addr) // Control register read
|
if (!read_address) // Control register read
|
o_wb_data <= { bw_reset_request,
|
o_bus_data <= { bw_reset_request,
|
bw_stopped,
|
bw_stopped,
|
bw_triggered,
|
bw_triggered,
|
bw_primed,
|
bw_primed,
|
bw_manual_trigger,
|
bw_manual_trigger,
|
bw_disable_trigger,
|
bw_disable_trigger,
|
(raddr == {(LGMEM){1'b0}}),
|
(raddr == {(LGMEM){1'b0}}),
|
bw_lgmem,
|
bw_lgmem,
|
full_holdoff };
|
full_holdoff };
|
else if (!bw_stopped) // read, prior to stopping
|
else if (!bw_stopped) // read, prior to stopping
|
o_wb_data <= i_data;
|
o_bus_data <= i_data;
|
else // if (i_wb_addr) // Read from FIFO memory
|
else // if (i_wb_addr) // Read from FIFO memory
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
o_bus_data <= nxt_mem; // mem[raddr+waddr];
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_data = o_bus_data;
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
|
|
|
reg br_level_interrupt;
|
reg br_level_interrupt;
|
initial br_level_interrupt = 1'b0;
|
initial br_level_interrupt = 1'b0;
|
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
|
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
|
&&(!br_level_interrupt);
|
&&(!br_level_interrupt);
|
always @(posedge i_wb_clk)
|
always @(posedge bus_clock)
|
if ((bw_reset_complete)||(bw_reset_request))
|
if ((bw_reset_complete)||(bw_reset_request))
|
br_level_interrupt<= 1'b0;
|
br_level_interrupt<= 1'b0;
|
else
|
else
|
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
|
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
|
|
|
|
// verilator lint_off UNUSED
|
|
// Make verilator happy
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wire [28:0] unused;
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assign unused = { i_wb_data[30:28], i_wb_data[25:0] };
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// verilator lint_on UNUSED
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endmodule
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endmodule
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No newline at end of file
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