| Line 70... |
Line 70... |
i_setup,
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i_setup,
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`endif
|
`endif
|
i_uart_rx, o_uart_tx);
|
i_uart_rx, o_uart_tx);
|
input i_clk;
|
input i_clk;
|
`ifndef OPT_STANDALONE
|
`ifndef OPT_STANDALONE
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input [29:0] i_setup;
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input [30:0] i_setup;
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`endif
|
`endif
|
input i_uart_rx;
|
input i_uart_rx;
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output wire o_uart_tx;
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output wire o_uart_tx;
|
|
|
`ifdef OPT_DUMBECHO
|
`ifdef OPT_DUMBECHO
|
| Line 100... |
Line 100... |
// data word, 1-stop bit, and no parity.
|
// data word, 1-stop bit, and no parity.
|
//
|
//
|
// This code only applies if OPT_DUMBECHO is not defined.
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// This code only applies if OPT_DUMBECHO is not defined.
|
`ifdef OPT_STANDALONE
|
`ifdef OPT_STANDALONE
|
wire [29:0] i_setup;
|
wire [29:0] i_setup;
|
assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz
|
assign i_setup = 31'd868; // 115200 Baud, if clk @ 100MHz
|
`endif
|
`endif
|
|
|
// Create a reset line that will always be true on a power on reset
|
// Create a reset line that will always be true on a power on reset
|
reg pwr_reset;
|
reg pwr_reset;
|
initial pwr_reset = 1'b1;
|
initial pwr_reset = 1'b1;
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| Line 126... |
Line 126... |
wire [7:0] rx_data;
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wire [7:0] rx_data;
|
|
|
rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
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rxuart receiver(i_clk, pwr_reset, i_setup, i_uart_rx, rx_stb, rx_data,
|
rx_break, rx_perr, rx_ferr, rx_ignored);
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rx_break, rx_perr, rx_ferr, rx_ignored);
|
|
|
|
// Bypass any transmit hardware flow control.
|
|
wire rts;
|
|
assign rts = 1'b1;
|
|
|
wire tx_busy;
|
wire tx_busy;
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txuart transmitter(i_clk, pwr_reset, i_setup, rx_break,
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txuart transmitter(i_clk, pwr_reset, i_setup, rx_break,
|
rx_stb, rx_data, o_uart_tx, tx_busy);
|
rx_stb, rx_data, rts, o_uart_tx, tx_busy);
|
|
|
`endif
|
`endif
|
|
|
endmodule
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endmodule
|
|
|
