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[/] [wbuart32/] [trunk/] [bench/] [verilog/] [echotest.v] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 55... Line 55...
// and external functionality of any UART, independent of the UART protocol.
// and external functionality of any UART, independent of the UART protocol.
//
//
`define OPT_DUMBECHO
`define OPT_DUMBECHO
//
//
//
//
// Uncomment the next line if you want this program to work as a standalone
// One issue with the design is how to set the values of the setup register.
// (not verilated) RTL "program" to test your UART.  You'll also need to set
// (*This is a comment, not a verilator attribute ... )  Verilator needs to
// your setup condition properly, though.  I recommend setting it to the 
// know/set those values in order to work.  However, this design can also be
// ratio of your onboard clock to your desired baud rate.  For more information
// used as a stand-alone top level configuration file.  In this latter case,
// about how to set this, please see the specification.
// the setup register needs to be set internal to the file.  Here, we use
 
// OPT_STANDALONE to distinguish between the two.  If set, the file runs under
 
// (* Another comment still ...) Verilator and we need to get i_setup from the
 
// external environment.  If not, it must be set internally.
//
//
 
`ifndef VERILATOR
`define OPT_STANDALONE
`define OPT_STANDALONE
 
`endif
//
//
module  echotest(i_clk,
module  echotest(i_clk,
`ifndef OPT_STANDALONE
`ifndef OPT_STANDALONE
                        i_setup,
                        i_setup,
`endif
`endif
Line 99... Line 104...
        // comms system from a 100MHz clock.  This also sets us to an 8-bit
        // comms system from a 100MHz clock.  This also sets us to an 8-bit
        // data word, 1-stop bit, and no parity.
        // data word, 1-stop bit, and no parity.
        //
        //
        // This code only applies if OPT_DUMBECHO is not defined.
        // This code only applies if OPT_DUMBECHO is not defined.
`ifdef  OPT_STANDALONE
`ifdef  OPT_STANDALONE
        wire    [29:0]   i_setup;
        wire    [30:0]   i_setup;
        assign          i_setup = 31'd868;      // 115200 Baud, if clk @ 100MHz
        assign          i_setup = 31'd868;      // 115200 Baud, if clk @ 100MHz
`endif
`endif
 
 
        // Create a reset line that will always be true on a power on reset
        // Create a reset line that will always be true on a power on reset
        reg     pwr_reset;
        reg     pwr_reset;

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